A method for forming a semiconductor device involves selecting a substrate on which a wurtzite III-nitride alloy layer will be formed, and a piezoelectric polarization and an effective piezoelectric coefficient for the wurtzite III-nitride alloy layer. It is determined whether there is a wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient. It is also determined whether there is a thickness for a layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization based on the selected substrate and the selected effective piezoelectric coefficient. Responsive to the determination that there is a wurtzite III-nitride alloy composition having a lattice constant satisfying the selected effective piezoelectric coefficient and a thickness for the layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization, the wurtzite III-nitride alloy layer is formed on the substrate having the wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient and having the thickness satisfying the selected piezoelectric polarization.

Atomic layer deposited (ALD) oxide semiconductors for integrated circuits are disclosed. In one aspect, an ALD process is used to form an oxide semiconductor channel formed from Indium Oxide (In.sub.2O.sub.3) on a transistor formed in a back end of line (BEOL) process. In further aspects, the thickness of the In.sub.2O.sub.3 is controlled to a desired thickness and annealed to reduce defects. Still further aspects of the present disclosure may use this process on a fin-based field-effect transistor (FinFET).

A wafer supporting mechanism including: a wafer supporting table; and a movable part supported by the wafer supporting table, wherein the wafer supporting table includes a wafer supporting portion for transfer that stands up from a first surface opposing a back surface of a wafer to be placed and is provided further toward an inner side than an outer peripheral edge of the wafer to be placed, and the movable part includes a wafer supporting portion for film formation that is positioned further toward an outer peripheral side of the wafer to be placed than the wafer supporting portion for transfer and is relatively movable with respect to the wafer supporting table in a standing direction of the wafer supporting portion for transfer.

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.

An Oxide TFT, a preparation method thereof, an array substrate and a display device are described. The method includes forming a gate electrode, a gate insulating layer, a channel layer, a barrier layer, as well as a source electrode and a drain electrode on a substrate; the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H.sub.2, Ar and O.sub.2. By depositing a channel layer in a first mixed gas containing H.sub.2, Ar and O.sub.2, the hysteresis phenomenon of the TFT can be mitigated effectively to improve the display quality of the display panel.

A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for metal films of a source electrode layer, a drain electrode layer, and a gate electrode layer, whereby diffusion of oxygen to the metal films is suppressed.

A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.

Provided is a SiC composite substrate including a biaxially-oriented SiC layer in which SiC is oriented in both a c-axis direction and an a-axis direction, and a SiC polycrystalline layer provided on one surface of the biaxially-oriented SiC layer. A joint interface of the biaxially-oriented SiC layer and the SiC polycrystalline layer has an uneven shape, which has an amount of unevenness of 1 to 200 μm.