Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA is a non-universal cutter.

A compound semiconductor device disclosed herein includes a substrate, an electron transit layer formed on the substrate, a compound semiconductor layer containing gallium and formed on the electron transit layer, a diffusion preventing layer containing gallium oxide and formed on the compound semiconductor layer, an insulation layer formed on the diffusion preventing layer, and a source electrode, a drain electrode, and a gate electrode formed over the electron transit layer at a distance from one another.

A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.

The present invention provides a conductive polymer composition including: (A) a -conjugated conductive polymer having at least one repeating unit shown by the following general formulae (1-1), (1-2), and (1-3); and (B) a dopant polymer which contains a repeating unit a shown by the following general formula (2) and has a weight-average molecular weight in a range of 1,000 to 500,000. The inventive conductive polymer composition has excellent antistatic performance in electron beam-resist drawing as well as good applicability onto a resist and peelability with H.sub.2O and an alkaline solution, thereby being suitably used for electron beam lithography. ##STR00001##

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of fine alignment of an e-beam tool includes projecting an electron image of a plurality of apertures of an e-beam column over an X-direction alignment feature of a wafer while moving the wafer along the Y-direction. The method also includes detecting a time-resolved back-scattered electron (BSE) detection response waveform during the projecting. The method also includes determining an X-position of every edge of every feature of the X-direction alignment feature by calculating a derivative of the BSE detection response waveform. The method also includes, subsequent to determining an X-position of every edge of every feature of the X-direction alignment feature, adjusting an alignment of the e-beam column to the wafer.

Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

The present disclosure provides a method that includes forming a first patternable material layer on a substrate; forming a second patternable material layer over the first patternable material layer; and performing a charged particle beam lithography exposure process to the first patternable material layer and the second patternable material layer, thereby forming a first latent feature in the first patternable material layer.

The present disclosure provides one embodiment of a method that includes slicing a first sub-polygon out of the pattern layout and writing the first sub-polygon onto the substrate using a beam with a first beam setting that is associated with the first sub-polygon. The method additional includes slicing a second sub-polygon out of the remaining pattern layout that does not include the first sub-polygon. The second sub-polygon interfaces with the first sub-polygon on at least one edge. Also, the method includes, without turning off the beam after writing the first sub-polygon onto the substrate, writing the second sub-polygon onto the substrate with a second beam setting that is associated with the second sub-polygon.

A resist film structure is provided, which allows a resist layer to have improved photosensitivity to EUV or electron beams without changing the photosensitivity of the resist material itself. A metal layer 1 with a thickness as small as a nanometer level is provided on a resist polymer layer 2 formed on a substrate 3. When the resist layer in this structure is exposed to light, the metal layer 1 produces a surface plasmon effect to enhance the irradiation to the resist film, so that the photosensitivity of the resist film is improved.

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.