A self-aligned GaN FinFET device and a method of fabricating the same are disclosed. This self-aligned process helps to fabricate GaN FinFET devices in a scalable manner. This work transforms the T-gate process to incorporate fins to further improve pinch-off and decrease leakage currents on highly scaled GaN HEMT structures. The GaN FinFET structure will also allow for integration of normally-off devices with normally-on devices by varying the fin width. The FinFET improvement combines the fin structure consisting of various fin pitches and widths, gate dielectric, self-aligned gate design, ultra-low ohmic contacts, and vertically scaled epitaxy into a single scalable process.

A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a column for an e-beam direct write lithography tool includes a first blanker aperture array (BAA) including a staggered array of openings having a pitch along an array direction. The array direction is orthogonal to a scan direction. Each opening has a first dimension in the array direction. The column also includes a second BAA including a staggered array of openings having the pitch along the array direction. Each opening has a second dimension in the array direction, the second dimension greater than the first dimension.

Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.

A resist underlayer film forming composition characterized by containing (A) a compound represented by formula (1) (in formula (1), independently, R.sup.1 represents a C1 to C30 divalent group; each of R.sup.2 to R.sup.7 represents a C1 to C10 linear, branched, or cyclic alkyl group, a C6 to C10 aryl group, a C2 to C10 alkenyl group, a thiol group, or a hydroxyl group; at least one R.sup.5 is a hydroxyl group or a thiol group; each of m.sup.2, m.sup.3, and m.sup.6 is an integer of 0 to 9; each of m.sup.4 and m.sup.7 is an integer of 0 to 8; m.sup.5 is an integer of 1 to 9; n is an integer of 0 to 4; and each of p.sup.2 to p.sup.7 is an integer of 0 to 2) and a cross-linkable compound represented by formula (2-1) or (2-2) (in formula (2), Q.sup.1 represents a single bond or an m.sup.12-valent organic group; each of R.sup.12 and R.sup.15 independently represents a C2 to C10 alkyl group or a C2 to C10 alkyl group having a C1 to C10 alkoxy group; each of R.sup.13 and R.sup.16 represents a hydrogen atom or a methyl group; each of R.sup.14 and R.sup.17 represents a C1 to C10 alkyl group or a C6 to C40 aryl group; n.sup.12 is an integer of 1 to 3; n.sup.13 is an integer of 2 to 5; n.sup.14 is an integer of 0 to 3; n.sup.15 is an integer of 0 to 3, with these ns having a relationship of 3(n.sup.12+n.sup.13+n.sup.14+n.sup.15)6; n.sup.16 is an integer of 1 to 3; n.sup.17 is an integer of 1 to 4; n.sup.18 is an integer of 0 to 3; n.sup.19 is an integer of 0 to 3, with these ns having a relationship of 2(n.sup.16+n.sup.17+n.sup.18+n.sup.19)5; and m.sup.12 is an integer of 2 to 10).

A multi-charged particle beam writing apparatus according to one aspect of the present invention includes a region setting unit configured to set, as an irradiation region for a beam array to be used, the region of the central portion of an irradiation region for all of multiple beams of charged particle beams implemented to be emittable by a multiple beam irradiation mechanism, and a writing mechanism, including the multiple beam irradiation mechanism, configured to write a pattern on a target object with the beam array in the region of the central portion having been set in the multiple beams implemented.

Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.