A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

An electron beam irradiation apparatus includes a first electrode being annular, arranged along the optical axis of the electron beam, at the downstream from the deflector, and in the magnetic field of the objective lens, to which a first potential being positive is variably applied, a second electrode being annular, arranged in the magnetic field of the objective lens and between the deflector and the first electrode, to which a second potential being positive and higher than the first potential is applied, and a third electrode being annular, arranged in the magnetic field of the objective lens and to be opposite to the second electrode with respect to the first electrode, to which a third potential lower than the first potential is applied.

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. A scan direction of the BAA is along a second direction, orthogonal to the first direction.

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.

A method for testing individual memory elements or sets of memory elements of an array of magnetic memory elements. The method involves forming a mask such as photoresist mask over an array memory elements. The mask is configured with an opening over each of the selected memory elements to be tested. The mask can be formed of photoresist which can be patterned by focused electron beam exposure to form opening at features sizes smaller than those available using standard photolithographic processes. An electrically conductive material is deposited over the mask and into the openings in the mask to make electrical contact with the selected memory element or memory elements to be tested. Then, electrical connection can be made with the electrically conductive material to test the selected one or more magnetic memory elements.

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. Particular embodiments are directed to implementation of an underlying absorbing and/or conducting layer for ebeam direct write (EBDW) lithography.