A method for fabricating semiconductor chip structures, which comprises steps of: providing plural slice units tiled with one another on a process carrier, wherein each slice unit is made from a wafer and includes a substrate with an outline, and a gap is formed between adjacent two of the slice units; planarizing tops of the slice units; accomplishing circuits on the slice units and turning them into circuited slice units; and forming plural semiconductor chip structures individually with each other by at least breaking down the circuited slice units; wherein a planar size of one slice unit is no less than that of a corresponding semiconductor chip structure, or the planar size of one slice unit is no less than multiple of the planar size of the corresponding semiconductor chip structure. A semiconductor carrier and a semiconductor chip structure made by the method are also provided.

The invention relates to a method for annealing of at least two wafers bonded via low-temperature direct bonding comprising heating the bonded wafers up to a first annealing temperature in the range of 100° C. to 500° C., preferably 150° C. to 400° C., even more preferred 150° C. to 200° C., holding the first annealing temperature in a range of 1 to 4 hours, preferably 1 to 3 hours, cooling down the bonded wafers to room temperature, re-heating the bonded wafers to a second annealing temperature in the range of 100° C. to 500° C., preferably 150° C. to 400° C., even more preferred 150° C. to 200° C., and cooling down the bonded wafers to room temperature.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

A device, a system and a method for bonding two substrates. A first substrate holder has a recess and an elevation.

A method for producing a stacked structure comprises: a) providing a carrier substrate and an initial substrate, each having a front face and a back face, b) forming a buried weakened plane in the carrier substrate or in the initial substrate, by implanting light ions through the front face of either of the substrates, c) joining the carrier substrate and the initial substrate via their respective front faces, d) thinning the initial substrate via its back face to form a donor substrate e) providing a receiver substrate having a front face and a back face, f) joining the donor substrate and the receiver substrate via their respective front faces, and g) separating along the buried weakened plane, so as to form the stacked structure comprising the receiver substrate and a surface film including all or part of a donor layer originating from the initial substrate.

A semiconductor device has a substrate. The substrate can be multiple layers. A first semiconductor layer made of a first semiconductor material is disposed over the substrate. The first semiconductor material can be substantially defect-free silicon carbide. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third layer can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.

A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.

A vacuumizing device includes a vacuum chamber, a bonding fixture and a vacuumizing system. The bonding fixture is disposed in the vacuum chamber and includes a substrate table provided with a plurality of grooves for retention of the substrate by suction. The vacuumizing system is disposed in communication with both the vacuum chamber and grooves. During vacuumizing by the vacuumizing system, a vacuum value in the grooves is smaller than or equal to a vacuum value in the vacuum chamber. In the vacuumizing device and methods, the vacuumizing system is used to vacuumize the grooves in the substrate table and the vacuum chamber so that the vacuum value in the grooves is always smaller than or equal to that in the vacuum chamber. As a result, the substrates are firmly retained on the substrate table without warping, thereby improving the quality of substrate bonding.

A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.