The present application discloses a method for manufacturing a superjunction trench gate MOSFET, wherein after a top metal layer is fully etched off using a photomask for etching the top metal layer and a second mask layer, the second mask layer is not removed. Etching continues on exposed metal tungsten in a source region source contact to fully etch off the exposed metal tungsten in the source region source contact, followed by removing the second mask layer, and then a second dielectric layer is formed, not only reducing mask layers to reduce manufacturing costs, but also avoiding short circuits caused by connection of the exposed metal tungsten in the source region source contact to other conductors. The exposure of metal tungsten can be avoided in the case of saving one mask layer, and the process risk is reduced.

Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.

The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical compounds, said method comprising the following steps: a step in which the electrically conductive substrate is placed in contact with chemical compounds comprising at least a disulfide terminal group; a step in which the disulfide terminal group of said chemical compounds is electro-oxidized, causing said chemical compounds to form a layer at the surface of the electrically conductive substrate.

Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.

A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy comprising components of the first metal layer, second metal layer, and the semiconductor substrate.

Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.

In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of copper.

Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.