Method for forming an electrical contact

Abstract

A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

Claims

1. A method for forming an electrical contact to a semiconductor structure, the method comprising: providing a semiconductor structure; providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region; and converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

2. The method according to claim 1, wherein said metal is nickel.

3. The method according to claim 1, wherein said vapor-solid reaction is carried out at a temperature in the range of 215 C. to 350 C.

4. The method according to claim 3, wherein said vapor-solid reaction is carried out at a temperature in the range of 215 C. to 250 C.

5. The method according to claim 4, wherein said germanium-comprising precursor is GeH.sub.4.

6. The method according to claim 3, wherein said vapor-solid reaction is carried out at a temperature in the range of 225 C. to 350 C.

7. The method according to claim 6, wherein said silicon-comprising precursor is SiH.sub.4.

8. The method according to claim 1, wherein said providing said semiconductor structure further comprises: producing a vertical semiconductor body protruding from said semiconductor substrate, wherein said vertical semiconductor body has a top surface and comprises said contact region on said top surface and wherein the method further comprises, before providing said metal, defining said area on said semiconductor structure.

9. The method according to claim 8, wherein said producing said vertical semiconductor body comprises depositing epitaxially a semiconductor material on a part of said semiconductor substrate.

10. The method according to claim 9, wherein said epitaxially deposited semiconductor material comprises Si, Ge or a Group III-V compound semiconductor.

11. The method according to claim 1, wherein said area exposes said semiconductor material at the bottom of a through-hole in an insulating layer and the method further comprises, after converting said metal, providing a contact metal in said through-hole.

12. The method according to claim 11, wherein said electrical contact has an upper interface with said contact metal and a lower interface, on said area, with said vertical semiconductor body and wherein said lower interface is planar and the thickness variation of said electrical contact between said upper interface and said lower interface is less than 1 nm.

13. The method according to claim 1, wherein said electrical contact is a NiGe or NiSi electrical contact.

14. The method according to claim 1, further comprising pre-treating the semiconductor structure prior to providing said metal.

15. The method according to claim 14, wherein said pre-treatment is a SiCoNi treatment.

16. The method according to claim 1, wherein said semiconductor material is InGaAs, GaAs or InAs.

17. The method according to claim 1, wherein the silicon-comprising precursor gas comprises a silicon halide, tetraethyl orthosilicate, hexamethyldisiloxane, tetraethylsilane, pentamethylsilane, hexamethyldisilane, tetramethylsilane, or methylsilane.

18. The method according to claim 1, wherein the germanium-comprising precursor gas comprises a germanium halide, digermane, trigermane, isobutylgermane, or tetramethylgermane.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1a is a flowchart representing a method according to an embodiment of the present invention.

(2) FIG. 1b is a flowchart representing a step of the method represented in the flowchart of FIG. 1a.

(3) FIG. 2 is a flowchart according to a particular embodiment of the method represented in the flowchart of FIG. 1a, where the step of defining an area on the semiconductor structure is introduced before the step of providing a metal on the area.

(4) FIG. 3 is Grazing Incidence X-Ray Diffraction (GIXRD) spectra of epitaxial Ge/Ni films that are (a) annealed and (b) GeH.sub.4 precursor treated at 225 C. and 250 C., respectively for 60 seconds.

(5) FIG. 4 is a comparison of the sheet resistance (R.sub.s) values at 225 C. and 250 C. for Si/epitaxial Ge/Ni stack annealed (tilted texture) and GeH.sub.4 exposed (dotted texture).

(6) FIG. 5 is a tilted view of a semiconductor structure according to a particular embodiment of the method represented in FIG. 2. (B indicates the direction of front view).

(7) FIGS. 6a to 6d show front view of the semiconductor structure represented in FIG. 5 according to a particular embodiment of the method represented in the flowchart of FIG. 2.

(8) FIGS. 7a and 7b show front view of the semiconductor structure represented in FIG. 5 according to an alternative embodiment of the method represented in the flowchart of FIG. 2.

(9) FIG. 8 shows parts (a) and (c) as a Transmission Electron Microscopy (TEM) image of a NiGe electrical contact produced by the state-of-the-art salmanide reaction and parts (b) and (d) are sketches of the TEM images shown in parts (a) and (d), respectively.

DETAILED DESCRIPTION OF THE INVENTION

(10) The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

(11) Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

(12) Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

(13) Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

(14) In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

(15) The following terms are provided solely to aid in the understanding of the invention.

(16) As used herein and unless provided otherwise, the term interface refers to a surface forming a common boundary between two materials that are in physical contact. In the present invention interface refers to the surface between the electrical contact and the vertical semiconductor body and to the surface between the contact metal and the electrical contact.

(17) As used herein and unless provided otherwise, the term planar refers to a surface being flat, e.g. being substantially in two dimensions.

(18) As used herein and unless provided otherwise, the term sheet resistance refers to the ratio of the resistivity of a material to its thickness. The unit of sheet resistance is usually taken as Ohms per square denoted as Ohms/sq., which is dimensionally equal to an Ohm, but is used for sheet resistance.

(19) As used herein and unless provided otherwise, the term front end of line (FEOL) refers to the first part of IC manufacturing where individual devices such as transistors, capacitors are present on the wafer.

(20) As used herein and unless provided otherwise, the term back end of line (BEOL) refers to the second part of IC manufacturing for interconnecting the individual devices, such as transistors, capacitors, present on a wafer. BEOL processing may comprise forming electrical contacts on source and drain regions, depositing a pre-metal dielectric (PMD), planarizing the PMD, forming contact holes in the PMD and providing a contact metal in these contact holes.

(21) As used herein and unless provided otherwise, the term electrical contact refers to a contact made on an area of a conducting or a semiconducting material.

(22) FIG. 1a is a flowchart representing a method according to an embodiment of the present invention.

(23) The method (100) starts with (110) providing a semiconductor structure (500). This semiconductor structure comprises a substrate (180).

(24) Thereafter, a metal (250) is provided (130) on an area of this semiconductor structure (500). This metal is, preferably, Ni. Providing (130) this metal (250) on an area of this semiconductor structure (500) typically comprises loading this semiconductor structure into a first tool. Typically, this first tool is a deposition tool. An in-situ pre-treatment is applied in this first tool that is subsequently followed by depositing this metal in the same chamber/tool. This pre-treatment is a dry pre-cleaning treatment. This dry pre-cleaning treatment is a SiCoNi treatment.

(25) This deposition can be done by any suitable deposition technique known to persons skilled in the art while paying attention to the thermal budget for Ni deposition. Any thermal budget in the range 30 C. (Room Temperature) to 200 C. would be ideal to avoid the interaction of Ni with underlying Ge during Ni deposition. Physical vapor deposition (PVD), sputtering or atomic layer deposition (ALD) may be used. More preferably, ALD is used since it provides conformal deposition.

(26) After depositing this metal (250) on an area of this semiconductor structure (500) in this first tool, this semiconductor structure is loaded into a second tool. Typically, this second tool is a deposition tool. This deposition tool may be a chemical vapor deposition (CVD) tool. When this semiconductor structure is placed on the chuck of this deposition tool, there is usually a temperature gradient due to the thickness of the semiconductor structure. Therefore, after loading, a stabilized temperature has to be reached between the chuck and the surface of this semiconductor structure. Thus, a stabilization time in the range of 30 to 60 seconds is required to reach this stabilized temperature.

(27) The inventors have found out that performing a vapor-solid reaction in the second tool (also referred to as vapor-liquid-solid (VLS) growth) converts this metal (250) to this Si-comprising (260) or this Ge-comprising alloy (260). This vapor-solid reaction is performed by subjecting this semiconductor structure including this metal in this second tool, once this stabilized temperature is reached, to a silicon-comprising precursor gas or a germanium-comprising precursor gas. This Si-comprising alloy is mono-nickel-silicide (NiSi). This Ge-comprising alloy is mono-nickel-germanide (NiGe).

(28) In an example the chamber pressure of the second tool is 4.2 Torr. The GeH.sub.4 gas is diluted with H.sub.2 to 10%. The gas flow rate of GeH.sub.4/H.sub.2 is 1700 sccm along with N.sub.2 diluent gas which was flown at 1500 sccm that corresponds to germane (GeH.sub.4) partial pressure of about 225 mTorr. The chosen GeH.sub.4 exposure time (60s) is sufficient enough to convert Ni to NiGe alloy.

(29) This silicon-comprising precursor gas may be, for example, halides of Si (SiCl.sub.4, SiBr4, SiCl.sub.2H.sub.2), tetraethyl orthosilicate (TEOS), hexamethyldisiloxane (HMDSO), tetraethylsilane, pentamethylsilane, hexamethyldisilane, tetramethylsilane, methylsilane.

(30) Preferably, this silicon-comprising precursor gas is SiH.sub.4.

(31) This germanium-comprising precursor gas may be, for example, halides of germanium (GeCl.sub.4, GeF.sub.2, GeBr.sub.2 etc), digermane, trigermane, isobutylgermane, tetramethylgermane.

(32) Preferably, this germanium-comprising precursor gas is GeH.sub.4.

(33) The reaction is aided by the interaction of Ni with GeH.sub.4 precursor as such or with the decomposed products of GeH.sub.4 precursor (for example: GeH.sub.4.fwdarw.GeH.sub.(4-x)+xH), the contribution of which depends on the processing temperature.

(34) Ni may catalyze the decomposition of each of these Ge-comprising precursors. However, the decomposition temperature may differ due to the fact that germanium is bonded to different H content, halides or to organic compounds having CH.sub.x that can vary the thermal stability and reactivity of the precursor. Furthermore, CH.sub.x bonded precursors may poison the Ni surface by carbon deposition. This can lead to a retardation in NiGe formation by hindering the mobility of both Ni and Ge. The thermal pyrolysis of Ge-organic compound at the higher temperature than the catalytic vapor-solid reaction temperature or at excessive VLS exposure time (at the same temperature) may lead to Ge incorporation (NiGe+Ge) that eventually may increase the sheet resistance of the electrical contact deteriorating the electrical properties.

(35) The use of GeH.sub.4, the simplest precursor from Ge family can alleviate the problems associated with the incorporation of halide or carbon impurities as mentioned above. This GeH.sub.4 precursor is diluted with H.sub.2 to reach 10% GeH.sub.4. This 10% GeH.sub.4 mixture containing H.sub.2 is provided into this second deposition chamber in the presence of a carrier gas. This carrier gas is an inert gas. Ar, He or N.sub.2 can be used as carrier gas. The purpose of using carrier gas is to regulate the partial pressure of germane precursor. This carrier gas is, preferably, N.sub.2.

(36) This vapor-solid reaction is carried out in a temperature range of 215 C. to 350 C. This temperature range is also indicative of the temperature range of this stabilized temperature.

(37) The inventors have found out that when GeH.sub.4 is used as germanium-comprising precursor gas, this vapor-solid reaction is carried out at a temperature in the range of 215 C. to 250 C. Preferably, this temperature is 225 C. This vapor-solid reaction leads to the formation of mono-nickel-germanide, NiGe. It is an advantage of vapor solid reaction that a low resistive, mono-nickel-germanide electrical contact is formed at a temperature of 225 C.

(38) By using a vapor-solid reaction that utilizes a germanium-comprising precursor, preferably GeH.sub.4, in the temperature range of 215 C. to 250 C., the selective etch step, which is essential in state-of-the-art salmanide process, is not required anymore and can be omitted. Furthermore, the lower temperature range of this vapor-solid reaction does not jeopardize the thermal budget when manufacturing a semiconductor device and might preserve the mobility of Ge. More advantageously, mono-nickel-germanide phase is obtained in a single step at this temperature range, which is lower than what is used in the state-of-the-art, resulting in an electrical contact having a sheet resistance value lower than 20 Ohms/sq.

(39) The inventors have found out that when SiH.sub.4 is used as silicon-comprising precursor gas, this vapor-solid reaction is carried out at a temperature in the range of 225 C. to 350 C. Preferably, this temperature is 325 C.350 C. This vapor-solid reaction leads to the formation of mono-nickel-silicide, NiSi, electrical contact.

(40) FIG. 1b is a flowchart representing a step of the method represented in the flowchart of FIG. 1a.

(41) The step of providing (110) a semiconductor structure (500) comprises providing (111) a semiconductor substrate (180).

(42) Providing (110) this semiconductor structure (500) further comprises producing (112) a vertical semiconductor body (175) protruding from this semiconductor substrate (180).

(43) In embodiments, this substrate (180) is a bulk Si substrate.

(44) In these embodiments, producing (112) this vertical semiconductor body (175) comprises patterning this bulk Si substrate and etching to, thereby, create free-standing pillars made from this substrate. An insulating layer (170) is deposited and planarized, thereby exposing the top surfaces of these free-standing pillars. This insulating layer is a shallow trench isolation layer (STI). This insulating layer is typically SiO.sub.2.

(45) This insulating layer is recessed, thereby revealing the top part of these pillars. This top part is a vertical semiconductor body made from Si. This vertical semiconductor body is a fin structure (175).

(46) Alternatively, after planarizing this insulating layer (170), these free-standing pillars may be recessed, thereby creating a recess exposing this semiconductor substrate (180). This recess is bounded by this insulating material (170). A vertical semiconductor body is, thereby, produced by epitaxially depositing another semiconductor material on a part of this semiconductor substrate that is exposed at bottom of this recess. This epitaxially deposited semiconductor material comprises Si, Ge or a group III-V compound semiconductor. This vertical semiconductor body is a fin structure (175). This vertical semiconductor body comprises Si, Ge or a group III-V compound semiconductor.

(47) In embodiments, where this substrate is a bulk Si substrate, an alternative option exists for producing this vertical semiconductor body. This alternative option comprises depositing epitaxially a semiconductor material on a part of this semiconductor substrate. This epitaxially deposited semiconductor material comprises Si, Ge or a group III-V compound semiconductor. In this alternative option, this part may be a complete (exposed) surface of this semiconductor substrate. Performing a patterning process and subsequently etching this epitaxially deposited semiconductor material, thereby creates this vertical semiconductor body. This vertical semiconductor body is a fin structure (175). This vertical semiconductor body thus, comprises Si, Ge or a group III-V compound semiconductor.

(48) In alternative embodiments, this substrate may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate comprising a silicon layer or a germanium layer present on an insulating layer, respectively.

(49) In these alternative embodiments, this fin structure is formed from the silicon layer or the germanium layer present on the insulating layer of the SOI or GeOI substrate, respectively by performing patterning and etching processes. Producing this fin structure in these alternative embodiments is known to persons skilled in the art.

(50) FIG. 2 is a flowchart according to a particular embodiment of the method represented in the flowchart of FIG. 1a. The method (300) starts with a first step (210). This first step (210) comprises the step of providing (111) a semiconductor substrate (180) and the step of producing (112) a vertical semiconductor body (l75) as outlined in FIG. 1b. This first step (210) further comprises defining (120) an area on this semiconductor structure (500).

(51) In embodiments defining an area on this semiconductor structure (500) comprises depositing an insulating layer (170) on this semiconductor structure. This insulating layer is preferably SiO.sub.2. This insulating layer may also be referred to as a Pre-Metal Dielectric (PMD). A chemical mechanical planarization step is performed, thereby planarizing the surface of this dielectric and reducing the thickness to a predetermined value. A photoresist is deposited on said semiconductor structure overlying this insulating layer. A lithographic process is performed, thereby creating a patterned photoresist. This lithographic process may be done by Deep UV (DUV), Extreme UV (EUV), Directed Self-Assembly (DSA) or any one of multiple patterning techniques such as Self-Aligned Double Patterning (SADP), Self-Aligned Quadruple Patterning (SAQP), Self-Aligned Triple Patterning (SATP). A subsequent etch process is performed using this patterned photoresist as a mask layer, thereby creating a through-hole (150) through this insulating layer (220). This through-hole is a contact hole (150, 150). The diameter (y) of this contact hole may be given by yx or by y(x+2t) where (x) is the spacer-to-spacer distance between two neighboring gate stacks (290) and (t) is the thickness of each spacer (190) present on each side of the gate electrode (160). However, in the latter situation, the diameter (y) of the contact hole (150,150) cannot be that large such that contact holes (150,150) on either side of a gate stack (290) are merged.

(52) This hole opens, at its bottom, to an area (240, 240) of this semiconductor structure (500). This area is located on the top surface of this vertical semiconductor body (175) comprised in this semiconductor structure. This area (240,240) exposes a semiconductor material and is at least a part of a contact region. This contact region is at least a part of a top surface of a source (280) and/or a drain region (270) comprised on the top part of this vertical semiconductor body (150). This area is a contact area.

(53) Defining this area further comprises removing this patterned photoresist by performing a strip process.

(54) In a second step (130) of the method (300), a metal (250) is provided on this area as outlined in FIG. 1a.

(55) In a third step (140) of the method (300), this metal (250) is converted to an alloy (260) as outlined in FIG. 1a.

(56) FIG. 3 compares the Grazing Incidence X-Ray Diffraction (GIXRD) spectra of Ni at 225 C. and 250 C. when (a) annealed and (b) subjected to GeH.sub.4 precursor. GIXRD spectra confirms that for both the studied temperatures, GeH.sub.4 treated Ni films show prominent signatures due to NiGe (FIG. 3, part b) while for the annealed ones only at 250 C., such peaks are observed (FIG. 3, part a). The presence of NiGe peaks at 225 C. for NiGeH.sub.4 approach, that is lacking for anneal provided samples, clearly confirms that the NiGe formation is due to the chemical reaction between Ni films and GeH.sub.4 precursor rather than the self-aligned reaction between Ni and Ge films. At 250 C., though both applied routes results in NiGe formation, sharp reflections for the GeH.sub.4 treated ones indicate the enhanced film crystallinity compared to anneal processed films.

(57) FIG. 4 is a comparison of the sheet resistance (R.sub.s) values at 225 C. and 250 C. for Si/epitaxial Ge/Ni stack annealed (tilted texture) and GeH.sub.4 exposed (dotted texture). In aggrement with the GIXRD results, lower Rs values (16.11-16.37 ohms/sq) with good uniformity (1=3.9%) are obtained only in the case of vapor-solid reaction in support of NiGe formation at 225-250 C. Low Rs values (21.85 ohms/sq) are obtained for the annealed films at 250 C., while at 225 C. increase of Rs values (53.4 ohms/sq) is observed compared to untreated reference Ni (48.97 ohms/sq). Though NiGe is formed at 250 C. in both strategies, Rs data highlight that good film quality, in terms of electrical properties, is possible only via vapor-solid reaction route. Relatively higher Rs (21.85 ohms/sq) values with high non-uniformity (1=8.9%) is noted for annealed films compared to VLS (16.37 ohms/sq, 1=3.9) at 250 C.

(58) FIG. 5 is a tilted view of a semiconductor structure (500) according to a particular embodiment of the method represented in FIG. 2. This semiconductor structure comprises a substrate (180). This substrate is a bulk Si substrate. An insulating layer (170) is present on this semiconductor substrate (180). This insulating layer, is an STI layer and is, preferably, SiO.sub.2. A vertical semiconductor body (175) protrudes from this semiconductor substrate. This vertical semiconductor body is a fin structure. This semiconductor structure (500) further comprises a (plurality of) gate stack(s) (290). This gate stack comprises a gate dielectric (not shown in the figures), a gate electrode (160) and (optionally) a gate cap (230). This gate dielectric conformally covers this fin structure. This gate electrode (160) is deposited directly on this gate dielectric and wraps around this fin structure (175). This gate cap, when present, is directly on this gate electrode. Choices suitable to be used as the gate dielectric, the gate electrode (160) are known to persons skilled in the art. This gate stack is sandwiched between insulating spacers (190). This gate cap (230) and insulating spacers (190) may be made from Si.sub.3N.sub.4, SiON, SiN or SiC.

(59) FIGS. 6a to 6d show front view (as seen from direction B in FIG. 5) of the semiconductor structure (500) represented in FIG. 5 according to a particular embodiment of the method represented in the flowchart of FIG. 2.

(60) FIG. 6a shows the front view of this semiconductor structure (500) as presented in FIG. 5.

(61) This semiconductor structure (500) comprises a substrate (180). An insulating layer (170) is present on this semiconductor substrate. A fin structure (175) protrudes from this semiconductor substrate. This semiconductor structure further comprises plurality of gate stacks (290). Each gate stack comprises a gate electrode (160) and spacers (190) on its lateral sides and a gate cap (230) on its top surface. Spacer-to-spacer distance between two adjacent gate stacks (290) is designated by x.

(62) FIG. 6b shows the front view of this semiconductor structure (500) after an area (240) has been defined on this semiconductor structure as represented by step (120) of FIG. 1a and FIG. 2.

(63) This area (240) exposes at least a part of a contact region comprised on a top surface of a vertical semiconductor body (175). This contact region is at least a part of a top surface of a source region (280) and/or a drain region (270). This area is exposed at the bottom of a through-hole (150) formed through this insulating layer (220). This insulating layer (220) is provided on this semiconductor structure (500). This through-hole is a contact hole. The diameter (y) of this contact hole is smaller than the spacer-to-spacer distance (x) between two neighboring gate stacks (290). This area (240) is a contact area located on the top surface of this vertical semiconductor body (175) comprised in this semiconductor structure (500). This semiconductor body (175) is a fin structure. An epi layer may be present on source region (280) and drain region (270). This epi layer may be an epitaxially grown Si layer or an epitaxially grown SiGe layer. In this case, this area (240) may be sloped.

(64) This through-hole has side walls (155) that bound this area (240). These side walls expose a part of at least one insulating material. This exposed part of this at least one insulating material is the insulating layer (220).

(65) FIG. 6c shows the front view of this semiconductor structure (500) after a metal layer (250) is provided at least on this area (240) of this semiconductor structure (500), in the first tool, as represented by step 130 of FIG. 1a and FIG. 2. As shown in this figure, this metal layer (250) is also provided on the exposed top surface (225) of this insulating layer (220) and on the side walls (155) of this through-hole (150). This metal is Ni.

(66) Alternatively, this metal may also be selectively provided only on this area (240) that exposes at least a part of a source (280) region and/or a drain region (270) comprised on the top surface of this vertical semiconductor body (175).

(67) Exposing this semiconductor structure (500) after Ni deposition, to a Si or Ge comprising precursor gas, in the second tool, converts Ni into a Si or Ge comprising alloy. This Si or Ge comprising alloy is a mono-nickel silicide or a mono-nickel-germanide (260). When this metal layer (250) is also provided on the exposed top surface (225) of this insulating layer (220) and on the side walls (155) of this through-hole (150), conversion of this metal into this Si comprising alloy or this Ge comprising alloy results in a continuous layer.

(68) On top of this mono-nickel-silicide or mono-nickel-germanide, another metal may be provided on this area of this semiconductor structure. It may also be a stack comprising several metals that are present for different purposes such as adhesion, to act as barrier or for tuning the work function.

(69) FIG. 6d shows a semiconductor device (501) obtained after contact fill metal (265) deposition and subsequently, a planarization step has been performed on this semiconductor structure (500). This contact metal (265) may be tungsten, copper, aluminum, cobalt or another low resistive metal that can be applied in a similar way.

(70) This planarization step is a chemical mechanical planarization (CMP) step. This CMP step is performed until an end point is reached, whereby this Si or Ge comprising alloy (260) has been removed to, thereby, expose a top surface (225) of this insulating layer (220). This Ge comprising alloy is a mono-nickel-germanide (NiGe). This Si comprising alloy is a mono-nickel-silicide (NiSi).

(71) An electrical contact is thus, formed on an area (240) of this semiconductor structure (500). At the bottom of this through-hole (150) this electrical contact has an upper interface with this contact metal (265) and a lower interface with this vertical semiconductor body (175) on this area (240). This lower interface is a planar interface. The thickness variation of this electrical contact between this upper interface and this lower interface is less than <1 nm.

(72) In the case where there may be an epitaxially grown Si layer or an epitaxially grown SiGe layer on the source region (280) and drain region (270) that results in a sloped area, this electrical contact still has a planar interface with this sloped area. The thickness variation of this electrical contact between this upper interface and this lower interface on this sloped area is less than 1 nm.

(73) FIGS. 7a and 7b show front view of the semiconductor structure (500) represented in FIG. 5 according to an alternative embodiment of the method represented in the flowchart of FIG. 2.

(74) In this alternative embodiment, as shown in FIG. 7a, the lithography and etch process used within the step (120) of defining an area on the semiconductor structure results in obtaining (through-holes) contact holes (150) having diameter (y) that is larger than the summation of spacer-to-spacer distance (x) between two neighboring gate stacks (290) and the total spacer thickness (2t) on both sides of this area (240). Even though the diameter of the contact hole (150) is larger than the summation of the spacer-to-spacer distance (x) between two neighboring gate stacks (290) and the total spacer thickness (2t) on both sides of this area (240), the diameter (y), in this case, cannot be that large such that contact holes (150) on either side of a gate stack (290) are merged.

(75) In this alternative embodiment, this contact hole (150) opens at its bottom to this area (240), where this area exposes the complete contact region present between two neighboring gate stacks (290) having a spacer-to-spacer (x) separation distance. This contact region is, then, the complete top surface of the source region (280) and/or drain region (270) present on the top part of this vertical semiconductor body (175). This vertical semiconductor body is a fin structure and this area (240) is a contact area.

(76) This area (240) is bounded by sidewalls (155). These sidewalls expose the insulating spacers (190). These exposed insulating spacers (190) are those that are present and face each other on opposite sides of two neighboring gate stacks (290). These sidewalls (155) of the contact hole (150) further expose this insulating layer (220).

(77) Ni (250) is provided conformally in the first tool covering the top surface (225) of this insulating layer (220), sidewalls (155) of this through-hole and this contact area (240)

(78) In this alternative embodiment shown in FIG. 7a, providing (130) this metal (250), which is Ni, as represented in flowchart according to FIG. 2 may also be done in a selective way to result in Ni being present only on this area (240).

(79) After subjecting Ni to a Si comprising precursor gas or a Ge comprising precursor gas in the second tool, Ni (250) is converted into a Si comprising or a Ge comprising alloy (260). This Ge comprising alloy is a mono-nickel-germanide (NiGe). This Si comprising alloy is a mono-nickel-silicide (NiSi).

(80) FIG. 7b, shows a semiconductor device (502) obtained after contact fill metal (265) deposition and subsequently, a planarization step has been performed on this semiconductor structure (500) presented in FIG. 7a.

(81) An electrical contact is formed on an area (240) of this semiconductor structure (500). At the bottom of this through-hole (150) this electrical contact has an upper interface with this contact metal (265) and a lower interface with this vertical semiconductor body (175) on this area (240). This lower interface is a planar interface. The thickness variation of this electrical contact between this upper interface and this lower interface is less than <1 nm.

(82) Alternatively (not shown in the figures), the lithography and etch process used within the step (120) of defining an area on the semiconductor structure may result in obtaining (through-holes) contact holes having diameter (y) that is equal to the spacer-to-spacer distance (x) between two neighboring gate stacks.

(83) Yet alternatively, the lithography and etch process used within the step (120) of defining an area on the semiconductor structure may result in obtaining contact holes having diameter (y) that is equal to the summation of spacer-to-spacer distance (x) between two neighboring gate stacks and the total spacer thickness (2t) on both sides of this horizontal portion.

(84) Parts (a) and (c) of FIG. 8 show Transmission Electron Microscopy (TEM) images of a mono-nickel-germanide (NiGe) electrical contact produced by the state-of-the-art salmanide process. Parts (b) and (d) of FIG. 8 are sketches of the TEM image presented in parts (a) and (b) of FIG. 8, respectively. This NiGe electrical contact (260) is formed on a fin structure (175) made of Ge on Si substrate (180). A contact metal (265), which is tungsten (W), is deposited on this NiGe electrical contact (260). It is noted that due to the non-uniform reaction between the deposited nickel and germanium, the interface between NiGe and Ge is not planar. Ni has reacted more with Ge on the left side of the fin structure (175) compared to the right side, thereby leading to the formation of a non-planar interface between NiGe and Ge. This has led to a thickness variation of (indicated by in parts (b) and (d) in FIG. 8 in the range of 10-15 nm of this NiGe/Ge interface between the left and the right side of the fin structure (175). A TiN layer (1) may be present between NiGe electrical contact (260) and W contact metal (265).

(85) Advantageously, the method described may be particularly suited for producing NiGe or NiSi electrical contacts to be used in an integrated circuit comprising multiple n-MOS and p-MOS transistors. This is because the method described simplifies the electrical contact formation process since NiGe or NiSi electrical contacts can be formed simultaneously on n-MOS and p-MOS transistors thanks to the advantage that NiGe or NiSi formation, by the method described, is independent of the material onto which Ni is provided.

(86) Alternatively, if, this p-MOS and this n-MOS transistor or plurality of n-MOS and p-MOS transistors is/are desired to have different electrical contacts, for example NiGe on p-MOS transistor and NiSi on n-MOS transistor or an opposite combination, then after Ni deposition, a protective layer is deposited on this semiconductor structure. This protective layer may be SiO2, SiN, amorphous carbon or other hard mask. This protective layer is patterned and etched, thereby, leaving this protective layer (only) on a second transistor area and exposing a first transistor area. This first transistor area is a p-MOS transistor area. This second transistor area is a n-MOS transistor area. Subjecting this semiconductor structure to a Ge comprising precursor gas at a temperature in the range of 215 C. to 250 C. forms NiGe electrical contact on this first transistor area. Thereafter, this protective layer is removed from this second transistor area. Then, this semiconductor structure is subjected to a Si comprising precursor gas at a temperature in the range of 225 C. to 350 C., to thereby form NiSi electrical contact on this second transistor area.

(87) Alternatively, after removing this protective layer from second transistor area and before subjecting this semiconductor structure to this Si comprising precursor gas, this first transistor area having NiGe electrical contact may be coated with this protective layer. Coating with this protective layer comprises depositing this protective layer, patterning and etching to thereby leave this protective layer on this first transistor area having NiGe electrical contact. This semiconductor structure is then subjected to this Si comprising precursor gas. This forms NiSi electrical contact on this second transistor area.