A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process.

A method for manufacturing an electronic device includes at least a step (1) of preparing a structure comprising (i) an adhesive film provided with a base material layer, an adhesive resin layer (A) provided on a first surface side of the base material layer, and an adhesive resin layer (B) provided on a second surface side of the base material layer, (ii) an electronic component attached to the adhesive resin layer (A) of the adhesive film, and (iii) a support substrate attached to the adhesive resin layer (B) of the adhesive film; a step (2) of sealing the electronic component with a sealing material; a step (3) of peeling the support substrate from the structure by reducing an adhesive force of the adhesive resin layer (B) by applying an external stimulus; and a step (4) of peeling the adhesive film from the electronic component.

Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.

A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.

A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.

Methods and equipment for the removal of semiconductor wafers grown on the top surface of a single crystal silicon substrate covered by a porous silicon separation layer by using IR irradiation of the porous silicon separation layer to initiate release of the semiconductor wafer from the substrate, particularly at edges (and corners) of the top surface of the substrate.

It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

In an embodiment, a plasma processing system includes a vacuum chamber, a substrate holder configured to hold a substrate to be processed where the substrate holder is disposed in the vacuum chamber. The system further includes an electron source disposed above a peripheral region of the substrate holder, the electron source being configured to generate an electron beam towards the peripheral region of the substrate holder.

In an embodiment, a plasma processing system includes a vacuum chamber, a substrate holder configured to hold a substrate to be processed where the substrate holder is disposed in the vacuum chamber. The system further includes an electron source disposed above a peripheral region of the substrate holder, the electron source being configured to generate an electron beam towards the peripheral region of the substrate holder.

A method of fabricating a semiconductor device is provided. The method includes forming a first fin structure which includes first semiconductor patterns and second semiconductor patterns stacked alternately on a substrate and extends in a first direction, forming an exposed first wire pattern group which includes the second semiconductor patterns by removing the first semiconductor patterns, heat-treating the exposed first wire pattern group, and forming a first gate electrode which surrounds the first wire pattern group and extends in a second direction different from the first direction.