The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure, etching first mask layer and second mask layer to expose a portion of a first semiconductor fin not covered by the first gate structure, performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion of the first semiconductor fin located below the first gate structure, etching the first semiconductor fin to remove a portion of an exposed portion of the first semiconductor fin, and epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first source region and a first drain region.

A semiconductor device includes a semiconductor substrate having a drift layer of a first conductivity type and a collector layer of a second conductivity type. A first buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the drift layer and the collector layer and a second buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the first buffer layer and the collector layer. A kurtosis of a peak of an impurity concentration of the second buffer layer is lower than a kurtosis of a peak of an impurity concentration of the first buffer layer.

The present invention provides a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation. Differing from conventional anti-fuse memory devices, the structure and fabrication of this NOI nonvolatile memory device are complied with currently-used standard COMS processes; that is, the NOI nonvolatile memory device provided by the present invention can be manufactured through the standard COMS processes, without using any additional masks for defining specific oxide layer. The most important is that, after the NOI nonvolatile memory device is treated with the anti-fuse operation, the Gate and Drain of the NOI nonvolatile memory device still propose the switching characteristic the same to the traditional MOSFET, resulting from the oxide breakdown caused by a high electric filed merely occur in an overlapped oxide segment of the gate oxide layer.

The present invention provides a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation. Differing from conventional anti-fuse memory devices, the structure and fabrication of this NOI nonvolatile memory device are complied with currently-used standard COMS processes; that is, the NOI nonvolatile memory device provided by the present invention can be manufactured through the standard COMS processes, without using any additional masks for defining specific oxide layer. The most important is that, after the NOI nonvolatile memory device is treated with the anti-fuse operation, the Gate and Drain of the NOI nonvolatile memory device still propose the switching characteristic the same to the traditional MOSFET, resulting from the oxide breakdown caused by a high electric filed merely occur in an overlapped oxide segment of the gate oxide layer.

Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.

Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.

A substrate support assembly includes a ceramic plate having an optical transmittance of at least 60% at a predetermined wavelength, the ceramic plate comprising a top surface and a bottom surface, wherein the top surface is to support a substrate. The substrate support assembly further includes a cooling base coupled to the bottom surface of the ceramic plate. The substrate support assembly further includes a light carrying medium disposed in the base, the light carrying medium to direct light having the predetermined wavelength onto the bottom surface of the ceramic plate, wherein a majority of energy from the light is to pass through the ceramic plate or light carrying medium attached inside holes of ceramic plate and be absorbed by the substrate.

A plasma processing apparatus includes: a processing container which defines a processing space; a microwave generator; a dielectric having an opposing surface which faces the processing space; a slot plate formed with a plurality of slots; and a heating member provided within the slot plate. The slot plate is provided on a surface of the dielectric at an opposite side to the opposing surface to radiate microwaves for plasma excitation to the processing space through the dielectric based on the microwaves generated by the microwave generator.

A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.