Patent classifications
H01L21/302
Method for etching metal or metal oxide by ozone water, method for smoothing surface of metal or metal oxide by ozone water, and patterning method using ozone water
Provided are a method for etching a metal or metal oxide without using a reagent, etc., that affects the environment, a method for smoothing a surface of a metal or metal oxide on an atomic level, and a method for patterning on an atomic level. Etching of a metal or metal oxide, or smoothing of a surface of a metal or metal oxide is possible using ozone water in which only ozone is dissolved. Patterning can also be performed by providing a metal that does not dissolve in the ozone water as a resist on a metal or metal oxide that can be etched by ozone water in which only ozone is dissolved, and etching using the ozone water.
Substrate processing method and control apparatus
Provided is a substrate processing method of filling a recess of a predetermined uneven pattern formed on a substrate with a film forming material by performing a first film forming processing, a first etching processing and a second film forming processing on the substrate, using a vertical substrate processing apparatus and a control apparatus controlling operations of the vertical substrate processing apparatus. The method includes calculating a first film forming condition, a first etching condition, and a second film forming condition by the control apparatus such that the film forming material is filled in the recess without any void after the second film forming processing; and performing the first film forming processing, the first etching processing and the second film forming processing on the substrate based on the calculated first film forming condition, first etching condition and second film forming condition.
Liquid composition and etching method for etching silicon substrate
An etching method includes etching a silicon substrate with a liquid composition containing an alkaline organic compound, water, and a boron compound with a content in the range of 1% by mass to 14% by mass. The boron compound is at least one of boron sesquioxide, sodium tetraborate, metaboric acid, sodium perborate, sodium borohydride, zinc borate, and ammonium borate.
Semiconductor device, FinFET transistor and fabrication method thereof
The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.
Methods employing sacrificial barrier layer for protection of vias during trench formation
A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.
Material property capacitance sensor
A system may include a controller configured to cause a capacitance probe to subject a material to a first electric signal having a first frequency and determine a first capacitance of the material at the first frequency. The controller is configured to cause the capacitance probe to subject the material to a second electric signal at a second frequency and determine a second capacitance of the material at the second frequency. The material includes at least a first constituent phase and a second constituent phase. The first constituent phase and the second constituent phase have substantially similar dielectric constants at the first frequency and substantially different dielectric constants at the second frequency. The controller is further configured to determine a porosity of the material based on the first capacitance and determine a relative phase composition of the first constituent phase and the second constituent phase based on the second capacitance.
Etching agent for copper or copper alloy
Object is to provide an etching solution which generates less foam and can etch copper or copper alloy at high selectivity when used in a step of etching copper or 5 copper alloy in an electronic substrate having both of copper or copper alloy and nickel. The etching solution to be used in a step of selectively etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel has, as essential components thereof, (A) a linear alkanolamine, (B) a chelating agent having an acid group in the molecule thereof, and (C) hydrogen peroxide.
Semiconductor device arrangement and a method for forming a semiconductor device arrangement
A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side.
Semiconductor device arrangement and a method for forming a semiconductor device arrangement
A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side.
Plasma etching method
A plasma etching method can form a hole having a required opening diameter in a silicon nitride layer, while suppressing a tip end portion of the hole from being narrowed. The plasma etching method includes a first process of supplying a processing gas containing oxygen and fluorocarbon into a plasma processing apparatus; and a second process of etching a silicon nitride layer 106a of a processing target object with a first mask 106 by exciting the processing gas into plasma. Further, the second process is performed in a state where an organic film ad generated from the processing gas is formed on an inner wall of an opening of the first mask 106 by gradually reducing a temperature of the processing target object from a first temperature T1 (80° C.) to a second temperature T2 (40° C.).