A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

A pattern forming method including: (a) forming a porous layer above an etching target layer; (b) forming an organic material with a transferred pattern on the porous layer; (c) forming, by use of the transferred pattern, a processed pattern in a transfer oxide film that is more resistant to etching than the porous layer; and (d) transferring the processed pattern to the etching target layer by use of the transfer oxide film as a mask.

When opaque films are deposited on semi-conductor wafers, underlying features may be concealed. In accordance with one implementation, such concealed features may be re-exposed via an ablation recovery process. One ablation recovery process entails aligning an energy source with a target position on a first surface of a semiconductor wafer based on position information retrieved from a second opposite surface of the semiconductor wafer, and firing a beam of the energy source to ablate opaque material at the target position and to expose a recovery feature underlying the opaque material.

When opaque films are deposited on semi-conductor wafers, underlying features may be concealed. In accordance with one implementation, such concealed features may be re-exposed via an ablation recovery process. One ablation recovery process entails aligning an energy source with a target position on a first surface of a semiconductor wafer based on position information retrieved from a second opposite surface of the semiconductor wafer, and firing a beam of the energy source to ablate opaque material at the target position and to expose a recovery feature underlying the opaque material.

Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

A method of etching a shallow trench is disclosed in the present invention. By removing the photoresist layer immediately at the end point of the hard mask layer etching and further using the improved process conditions etch the top of the substrate at the same time of the hard mask layer over-etching, such as a lower bias power, a higher pressure and a bigger polymer gases flow rate, the present invention has formed a smooth morphology on the top of the shallow trench. Therefore, the sharp corner appeared in the prior art is avoided by changing the start point of the silicon substrate etching, so as to fundamentally eliminate the leakage current caused by the sharp corner.

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

In a method of manufacturing a semiconductor device, a mask layer and a first layer may be sequentially formed on a substrate. The first layer may be patterned by a photolithography process to form a first pattern. A silicon oxide layer may be formed on the first pattern. A coating pattern including silicon may be formed on the silicon oxide layer. The mask layer may be etched using a second pattern as an etching mask to form a mask pattern, and the second pattern may includes the first pattern, the silicon oxide layer and the coating pattern. The mask pattern may have a uniform size.

Provided is a surface treatment method for a SiC substrate (40), the method being capable of controlling whether to generate a step bunching or the type of step bunching that is generated. In the surface treatment method in which the surface of the SiC substrate (40) is etched by heating the SiC substrate (40) under Si vapor pressure, an etching mode and an etching depth which are determined at least on the basis of an etching rate, are controlled to etch the SiC substrate (40), so that a surface pattern of the SiC substrate (40) after etching treatment is controlled.