A method for manufacturing a semiconductor device includes the following steps. A channel layer and a barrier layer are sequentially formed on a substrate by an epitaxial process to form a semiconductor device. The channel layer includes a first III-V compound and the barrier layer includes a second III-V compound. The semiconductor device is disposed within a cavity. A high-pressure fluid is introduced into the cavity to perform a passivation treatment on defects of the semiconductor device with the high-pressure fluid. The high-pressure fluid is doped with a compound composed of at least one of nitrogen, oxygen, and fluorine.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A semiconductor structure and a method for forming a semiconductor structure are provided. In some embodiments, a method is provided. The method includes following operations. A sacrificial gate structure is formed over a fin structure. The sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer. The sacrificial gate layer is removed to form a gate trench exposing the sacrificial dielectric layer. A doped region is formed in the fi structure covered by the sacrificial dielectric layer. The sacrificial dielectric layer, a portion of the doped region and a portion of the fin structure are removed from the gate trench. An interfacial layer is formed over the fin structure in the gate trench.

A silicon carbide (carborundum) semiconductor device and a manufacturing method thereof. The manufacturing method of the silicon carbide semiconductor device comprises the following steps of: providing a semiconductor component structure on a silicon carbide substrate, the semiconductor component structure being formed on a front side of the silicon carbide substrate; and forming a multi-layer structure on a back side of the silicon carbide substrate, the multi-layer structure comprising a plurality of ohmic contact layers and a plurality of gettering material layers. By dispersing the gettering material into multiple layers, and by adjusting a thickness combination of the ohmic contact layer and the gettering material layer, even if the gettering material layer is relatively thin (thickness sufficient for balling), a content is still sufficient for gettering carbon and reducing carbon aggregation and accumulation.

A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

The present invention relates to a trench-gate SiC MOSFET device and a manufacturing method therefor. The trench-gate SiC MOSFET device of the present invention comprises: a gate oxide film covering a gate trench formed in a SiC substrate (e.g., an n-type 4H-SiC substrate); a doped well (e.g., BPW) formed in a bottom region of the gate trench; a gate electrode formed in the gate trench covered by the gate oxide film; an interlayer insulating film formed on the gate electrode; a source electrode covering the top surface of a doping layer for a source area formed on the entire surface of an epitaxial layer of the substrate and the top surface of the interlayer insulating film; and a drain electrode formed on the rear surface of the substrate.

A semiconductor device includes a semiconductor layer having a first surface and a second surface, an element structure formed on the first surface side of the semiconductor layer and including a first conductivity type first region and a second conductivity type second region in contact with the first region, a gate electrode opposing the second region with a gate insulating film therebetween, a first conductivity type third region formed in the semiconductor layer to be in contact with the second region, and a first electrode formed on the semiconductor layer and electrically connected to the first region and the second region, in which the element structure includes a first and a second element structure, the first element structure is separated from the second region in a direction along the first surface of the semiconductor layer, and includes a second conductivity type first column layer extending in a thickness direction.

A method produces a single-crystal silicon semiconductor wafer. A single-crystal silicon substrate wafer is double side polished. A front side of the substrate wafer is chemical mechanical polished (CMP). An epitaxial layer of single-crystal silicon is deposited on the front side of the substrate wafer. A first rapid thermal anneal (RTA) treatment is performed on the coated substrate wafer at 1275-1295° C. for 15-30 seconds in argon and oxygen, having oxygen of 0.5-2.0 vol %. The coated substrate wafer is then cooled at or below 800° C., with 100 vol % argon. A second RTA treatment is performed on the coated substrate wafer at a 1280-1300° C. for 20-35 seconds in argon. An oxide layer is removed from a front side of the coated substrate wafer. The front side of the coated substrate wafer is polished by CMP.

An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1×10.sup.17 atoms/cm.sup.3.