Articles including a glass-based substrate with holes, semiconductor packages including an article with holes, and methods of fabricating holes in a substrate are disclosed. In one embodiment, an article includes a glass-based substrate having a first surface, a second surface, and at least one hole extending from the first surface. The at least one hole has an interior wall having a surface roughness R.sub.a that is less than or equal to 1 m. The at least one hole has a first opening having a first diameter that is present the first surface. A first plane is defined by the first surface of the glass-based substrate based on an average thickness of the glass-based substrate. A ratio of a depression depth to the first diameter of the at least one hole is less than or equal to 0.007.

The present invention provides a silicon nitride circuit board in which metal plates are attached on front and rear sides of a silicon nitride substrate having a three-point flexural strength of 500 MPa or higher, wherein assuming that a thickness of the metal plate on the front side is denoted by t1, and a thickness of the metal plate on the rear side is denoted by t2, a numerical relation: |t1t2|0.30 mm is satisfied, and a warp is formed in the silicon nitride substrate so that the silicon nitride substrate is convex toward the metal plate on one of the front side or the rear side; and warp amounts of the silicon nitride substrate in a long-side direction and a short-side direction both fall within a range from 0.01 to 1.0 mm. It is preferable that a longitudinal width (L1) of the silicon nitride substrate falls within a range from 10 to 200 mm, and a transverse width (L2) of the silicon nitride substrate falls within a range from 10 to 200 mm. Due to above structure, even if the silicon nitride circuit board has a large difference in thickness between the metal plates attached on front and rear sides of the silicon nitride substrate, TCT properties can be greatly improved.

Ceramic boards with thermal expansion similar to that of silicon can be used to support semiconductor chips in a fan out wafer level packaging process. The ceramic board can include sintered ceramic sheets with embedded vias and interconnect lines, together with passive components such as resistors, capacitors and inductors.

A wiring board includes an insulating substrate that is rectangular in a plan view, a plurality of mount electrodes arranged to face each other on a first main surface of the insulating substrate along a pair of opposing sides of the insulating substrate in a plan view, a plurality of terminal electrodes arranged to face each other on a second main surface of the insulating substrate along the pair of opposing sides of the insulating substrate in a perspective plan view, and an inner metal layer arranged inside the insulating substrate and extending in a direction perpendicular to the pair of opposing sides of the insulating substrate in a perspective plan view.

An electronic element mounting substrate includes a base body, an electrode, and a pad. The base body has a frame shape, and includes a first frame section and a second frame section, the second frame section being disposed on the first frame section and including an inner surface protruding further inward than an inner surface of the first frame section. The electrode is disposed on a bottom surface of the first frame section of the base body. The pad is disposed on a bottom surface of a protruding part of the second frame section, and is electrically connected to the electrode. A groove extending in a vertical direction is formed in an inner surface of the protruding part of the second frame section of the base body.

A conductive thin-film thinner than the undersurface electrode is provided outside the undersurface electrode on the undersurface of the ceramic substrate and connected to the undersurface electrode. A length from an outer circumferential part of the undersurface electrode to an outer circumferential pert of the ceramic substrate is equal to a length from an outer circumferential part of the top surface electrode to an outer circumferential part of the ceramic substrate. A thickness of the conductive thin-film is half or less than a thickness of the ceramic substrate.

Methods for obtaining a free-standing thick (>5 ?m) epitaxial material layer or heterostructure stack and for transferring the thick epitaxial layer or stack to an arbitrary substrate. A thick epitaxial layer or heterostructure stack is formed on an engineered substrate, with a sacrificial layer disposed between the epitaxial layer and the engineered substrate. When the sacrificial layer is removed, the epitaxial layer becomes a thick freestanding layer that can be transferred to an arbitrary substrate, with the remaining engineered substrate being reusable for subsequent material layer growth. In an exemplary case, the material layer is a GaN layer and can be selectively bonded to an arbitrary substrate to selectively produce a Ga-polar or an N-polar GaN layer.

An insulated metal substrate (IMS) and a method for manufacturing the same are disclosed. The IMS includes an electrically conductive line pattern layer, an encapsulation layer, a first adhesive layer, a second adhesive layer, and a heat sink element. The encapsulation layer fills a gap between a plurality of electrically conductive lines of the electrically conductive line pattern layer. An upper surface of the encapsulation layer is flush with an upper surface of the electrically conductive line pattern layer. The first and second adhesive layer are disposed between the electrically conductive line pattern layer and the heat sink element. A bonding strength between the first adhesive layer and the second adhesive layer is greater than 80 kg/cm.sup.2.

A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.