H01L21/4807

Methods for Forming Ceramic Substrates with Via Studs
20170338127 · 2017-11-23 ·

This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of the semiconductor devices.

Bonded structure and production method therefor

The deterioration of the resin base materials in the bonded structure is prevented. In a bonded structure containing two base materials at least one of which is a resin, an oxide which contains either P or Ag, V, and Te, and are formed by softening on the two base materials, bond the two base materials. In addition, in a method for producing a bonded structure containing two base materials at least one of which is a resin containing: supplying an oxide containing either P or Ag, V, and Te to the base material; and applying electromagnetic waves to the oxide, whereby the oxide, which soften on the substrates, bond the two base material.

THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL INTEGRATION AND METHOD OF MAKING THE SAME
20170243803 · 2017-08-24 ·

A thermally enhanced semiconductor assembly with three dimensional integration includes a semiconductor chip electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the semiconductor chip is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the semiconductor chip and the wiring board for interconnecting the semiconductor chip to terminal pads provided in the wiring board.

Method of manufacturing hexagonal boron nitride laminates
20170239854 · 2017-08-24 ·

A method of manufacturing hexagonal boron nitride laminates contains steps of: a) Dissolving dielectric polymers in solvent. b) Mixing h-BN powder to form a well-mixed h-BN coating slurry. c) Coating slurry on substrates and dried at 100 to 150° C. d-1) For free standing h-BN film, peel off h-BN dielectric polymer layer from substrate in water batch by roll to roll process. d-2) For h-BN film on substrates, heat compression of the substrates and hBN laminates at 100 to 250° C. for multi-layer structures. Thereby, hexagonal boron nitride laminates exhibit thermal conductivity of 10 to 40 W/m.Math.K, which is significantly larger than that currently used in thermal management. In addition, thermal conductivity of hexagonal boron nitride laminates increases with the increasing mass density, which opens a way of fine tuning of its thermal properties.

Ceramic-metal substrate with low amorphous phase

A ceramic-metal substrate in which the ceramic substrate has a low content of an amorphous phase. The ceramic-metal substrate includes a ceramic substrate and on at least one side of the ceramic substrate a metallization. The ceramic-metal substrate has at least one scribing line, at least one cutting edge, or both at least one scribing line and at least one cutting edge. Amorphous phases extend parallel to the scribing line and/or the cutting edge in a width of at most 100 μm or of at least 0.50 μm.

Wafer level stacked structures having integrated passive features

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

Mechanically Stable, Thermally Conductive And Electrically Insulating Stack For Mounting Device
20170229370 · 2017-08-10 ·

A mounting device for mounting electronic components, wherein the mounting device comprises a stack, in particular a layer stack configured as alternating sequence of at least one support structure for providing mechanical support and a plurality of thermally conductive and electrically insulating structures.

INSULATED METAL SUBSTRATE AND METHOD FOR MANUFACTURING SAME
20220270950 · 2022-08-25 ·

An insulated metal substrate (IMS) and a method for manufacturing the same are disclosed. The IMS includes an electrically conductive line pattern layer, an encapsulation layer, a first adhesive layer, a second adhesive layer, and a heat sink element. The encapsulation layer fills a gap between a plurality of electrically conductive lines of the electrically conductive line pattern layer. An upper surface of the encapsulation layer is flush with an upper surface of the electrically conductive line pattern layer. The first and second adhesive layer are disposed between the electrically conductive line pattern layer and the heat sink element. A bonding strength between the first adhesive layer and the second adhesive layer is greater than 80 kg/cm.sup.2.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
20210384109 · 2021-12-09 · ·

A semiconductor device includes a base body, a semiconductor chip deposited on a top surface of the base body, an encapsulating resin covering the base body and the semiconductor chip, a ring-shaped plug, and at least one stand-up terminal. The ring-shaped plug has an insulating property, is buried in a part of an upper part of the encapsulating resin while being aligned with respect to the base body, and has a top surface exposed to an outside of the encapsulating resin. The at least one stand-up terminal includes a vertical part penetrating the ring-shaped plug and extending in a direction perpendicular to the top surface of the base body, and has a lower end electrically connected to an electrode of the semiconductor chip inside the encapsulating resin and an upper end exposed to the outside of the encapsulating resin. The ring-shaped plug is fixed and bonded to a circumference of a side surface of the vertical part of the stand-up terminal.

Transferring Large-Area Group III-Nitride Semiconductor Material and Devices to Arbitrary Substrates

Methods for obtaining a free-standing thick (>5 μm) epitaxial material layer or heterostructure stack and for transferring the thick epitaxial layer or stack to an arbitrary substrate. A thick epitaxial layer or heterostructure stack is formed on an engineered substrate, with a sacrificial layer disposed between the epitaxial layer and the engineered substrate. When the sacrificial layer is removed, the epitaxial layer becomes a thick freestanding layer that can be transferred to an arbitrary substrate, with the remaining engineered substrate being reusable for subsequent material layer growth. In an exemplary case, the material layer is a GaN layer and can be selectively bonded to an arbitrary substrate to selectively produce a Ga-polar or an N-polar GaN layer.