A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.

An integrated ultraviolet (UV) detector includes a silicon carbide (SiC) substrate, supporting metal oxide field effect transistors (MOSFETs), and PN Junction photodiodes. The MOSFET includes a first drain/source implant in the SiC substrate and a second drain/source implant in the SiC substrate. The P-N junction photodiodes include a blanket oxide over the silicon carbide substrate and the gate, an implant extending into the silicon carbide substrate, and an opening extending through the blanket oxide layer down to the silicon carbide substrate on one side of the gate of the P-N junction photodiode.

According to one embodiment, a method of producing a SiC laminate having a hexagonal SiC layer and a 3C-SiC layer comprises: forming a seed plane parallel to a close-packed plane of the crystal lattice on the surface of the hexagonal SiC layer; providing an inclined plane, which is inclined with respect to the seed plane, to all faces adjacent to the seed plane; forming a two-dimensional nucleus of 3C-SiC on the seed plane; and epitaxially growing both the two-dimensional nucleus of 3C-SiC and the SiC layers exposed on the inclined plane simultaneously in a direction parallel to the close-packed plane of the crystal lattice.

An inverter circuit is connected serially with a first silicon carbide MOSFET and a second silicon carbide MOSFET. During a dead time when the first silicon carbide MOSFET and the second silicon carbide MOSFET are OFF, transient current of at least 100 A/cm2 flows in a built-in diode of the first silicon carbide MOSFET and a built-in diode of the second silicon carbide MOSFET.

A method for making an integrated device that includes a plurality of planar MOSFETs, includes forming a plurality of doped body regions in an upper portion of a silicon carbide substrate composition and a plurality of doped source regions. A first contact region is formed in a first source region and a second contact region is formed in a second source region. The first and second contact regions are separated by a JFET region that is longer in one planar dimension than the other. The first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region.

A semiconductor device includes a MOS structure part and first to third temperature sensing portions. The MOS structure part has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, and gate electrodes provided in the trenches via a gate insulating film. The first to the third temperature sensing portions are provided in plural and each includes the semiconductor substrate, the first semiconductor layer, a temperature sensing trench, a first polysilicon layer of the first conductivity type and a second polysilicon layer of the second conductivity type provided in the temperature sensing trench via an insulating film, a cathode electrode connected to the first polysilicon layer, and an anode electrode connected to the second polysilicon layer.

An electric assembly includes an insulated gate bipolar transistor device, a wide-bandgap transistor device electrically connected in parallel with the bipolar transistor device and a control circuit. The control circuit is electrically coupled to a gate terminal of the bipolar transistor device and to a control terminal of the wide-bandgap transistor device. The control circuit is configured to turn on the bipolar transistor device and to turn on the wide-bandgap transistor device at a predefined turn-on delay with respect to a turn-on of the bipolar transistor device.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A method for manufacturing a self-biased circulator includes cooling a nanocomposite material to a magnetization temperature below 200 K, applying an external magnetic field to the nanocomposite material to form a magnetic nanocomposite material, providing the magnetic nanocomposite material in a semiconductor substrate, and providing one or more metal layers over the magnetic nanocomposite material to form a circulator. By cooling and then magnetizing the nanocomposite material, a performance of the circulator may be significantly improved.