Disclosed is a transistor including a substrate, first and second type wells in contact with each other on the substrate; and a breakdown voltage improving region including vertical high concentration doped regions according to first and second types vertically in contact from upper surfaces of the first and second type wells to an upper surface of the substrate in a portion where the first and second type wells are in contact with each other.

A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate.

An integrated device and a method for making said integrated device. The integrated device includes a plurality of planar MOSFETs that have a first contact region formed in a first source region of a plurality of source regions and a second contact region formed in a second source region of the plurality of source regions. The first and second contact regions have respective portions of the source region doped with the second conductivity type, and the first and second contact regions are separated by a JFET region, wherein the JFET region is longer in one planar dimension than the other and the first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region.

A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A method for processing a crystalline substrate to form multiple patterns of subsurface laser damage facilitates subsequent fracture of the substrate to yield first and second substrate portions of reduced thickness. Multiple (e.g., two, three, or more) groups of parallel lines of multiple subsurface laser damage patterns may be sequentially interspersed with one another, with at least some lines of different groups not crossing one another. Certain implementations include formation of multiple subsurface laser damage patterns including groups of parallel lines that are non-parallel to one another, but with each line remaining within 5 degrees of perpendicular to the <1120> direction of a hexagonal crystal structure of a material of the substrate. Further methods involve formation of initial and subsequent subsurface laser damage patterns that are centered at different depths within an interior of a substrate, with the subsurface laser damage patterns being registered with one another and having vertical extents that are overlapping.

A method for forming semiconductor devices includes: grinding a backside of a semiconductor wafer with a grinding wheel during a first time interval, wherein the grinding wheel is forward moved during the first time interval, wherein a plurality of semiconductor devices are formed on the semiconductor wafer; and polishing the backside of the semiconductor wafer with the grinding wheel in a second time interval, wherein the grinding wheel is backward moved during the second time interval.

A method for manufacturing a self-biased circulator includes cooling a nanocomposite material to a magnetization temperature below 200 K, applying an external magnetic field to the nanocomposite material to form a magnetic nanocomposite material, providing the magnetic nanocomposite material in a semiconductor substrate, and providing one or more metal layers over the magnetic nanocomposite material to form a circulator. By cooling and then magnetizing the nanocomposite material, a performance of the circulator may be significantly improved.

An integrated ultraviolet (UV) detector includes a silicon carbide (SiC) substrate, supporting metal oxide field effect transistors (MOSFETs), Schottky photodiodes, and PN Junction photodiodes. The MOSFET includes a first drain/source implant in the SiC substrate and a second drain/source implant in the SiC substrate. The Schottky photodiodes include another implant in the SiC substrate and a surface metal area configured to pass UV light.