A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

This semiconductor device is provided with: a substrate which has, on a principal surface thereof, an input unit for inputting an alternating current power from the exterior, a ground connection unit for connecting to ground formed on the exterior, an output unit for outputting a post-adjustment direct current power to the exterior, and a semiconductor layer; a first Schottky barrier diode formed in a first region of the semiconductor layer so that a cathode electrode is connected to the input unit and so that an anode electrode is connected to the ground connection unit; a second Schottky barrier diode formed in a second region of the semiconductor layer so that a cathode electrode is connected to the output unit and so that an anode electrode is connected to the input unit; and a third Schottky barrier diode formed in a third region of the semiconductor layer so that a cathode electrode is connected to the output unit and so that an anode electrode is connected to the ground connection unit.

Input unit to which a voltage is applied, current output unit that outputs a high level current or a low level current in response to the voltage applied to input unit, and stochastic circuit unit that, in response to the voltage applied to input unit, changes a probability that the high level current or the low level current is output from current output unit, in accordance with a sigmoid function used in a mathematical model of a neural activity are included.

Input unit to which a voltage is applied, current output unit that outputs a high level current or a low level current in response to the voltage applied to input unit, and stochastic circuit unit that, in response to the voltage applied to input unit, changes a probability that the high level current or the low level current is output from current output unit, in accordance with a sigmoid function used in a mathematical model of a neural activity are included.

A stack-type semiconductor device includes: a first nanosheet stack structure arranged on a substrate; a first source/drain region extending on a side surface of the first nanosheet stack structure; a second nanosheet stack structure stacked on the first nanosheet stack structure; a second source/drain region extending on a side surface of the second nanosheet stack structure; a contact hole adjacent to a side surface of the second source/drain region and a side surface of the first source/drain region and extending in a vertical direction with respect to a surface of the substrate; and a contact electrode disposed in the contact hole, wherein the contact electrode contacts the side surface of the first source/drain region.

A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.

A 3D integrated circuit, the circuit including: a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second level is bonded to the first level, where the bonded includes metal to metal bonding, where the bonded includes oxide to oxide bonding, and where at least one of the second transistors include a replacement gate.

A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.

A switch circuit includes: a plurality of semiconductor elements (10) connected in series to each other; capacitive elements connected to at least some semiconductor elements (10) among the plurality of semiconductor elements (10); and a resistance element (30) connected between the capacitive elements.