A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

An endoscope device includes: an imaging unit including a semiconductor chip including an image sensor formed thereon, and a protective glass adhered on the image sensor with an adhesive layer; and a holder configured to hold the imaging unit by fitting the protective glass therein. The semiconductor chip includes: a light-receiving section; a peripheral circuit section; a guard ring surrounding the light-receiving section and the peripheral circuit section; and a plurality of metal dots formed on an outer circumference of the guard ring. The protective glass is adhered to the semiconductor chip by the adhesive layer so as to cover the light-receiving section, the peripheral circuit section, the guard ring, and the metal dots, and the metal dots are formed at a same interval from the outer circumference of the guard ring to a connection end portion of a connecting surface between the semiconductor chip and the protective glass.

Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries.

According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries.

[Problem] Provided is an oxide dielectric having superior properties, and a solid state electronic device (for example, a high pass filter, a patch antenna, a capacitor, a semiconductor device, or a microelectromechanical system) including the oxide dielectric.

[Solution] The oxide layer 30 according to the present invention includes an oxide (possibly including inevitable impurities) consisting essentially of bismuth (Bi) and niobium (Nb) and having a crystal phase of the pyrochlore-type crystal structure, in which the number of atoms of the above niobium (Nb) is 1.3 or more and 1.7 or less when the number of atoms of the above bismuth (Bi) is assumed to be 1.

An analog-to-digital converter includes a comparator having paired differential input ends, and a first capacitor and a second capacitor each provided at respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.

An analog-to-digital converter includes a comparator having paired differential input ends, and a first capacitor and a second capacitor each provided at respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.

A semiconductor device includes: a first power semiconductor element; a second power semiconductor element that is connected in parallel with the first power semiconductor element; a voltage changing unit that changes a voltage applied to a control terminal of the first power semiconductor element when the second power semiconductor element is turned on; a detection unit that detects a current flowing in the first power semiconductor element when the voltage changing unit has changed the voltage applied to the control terminal of the first power semiconductor element; and a temperature estimation unit that estimates a temperature of the first power semiconductor element based on a characteristic of the change of the current of the first power semiconductor element with respect to a change of the voltage applied to the first power semiconductor element.

A semiconductor device includes: a first power semiconductor element; a second power semiconductor element that is connected in parallel with the first power semiconductor element; a voltage changing unit that changes a voltage applied to a control terminal of the first power semiconductor element when the second power semiconductor element is turned on; a detection unit that detects a current flowing in the first power semiconductor element when the voltage changing unit has changed the voltage applied to the control terminal of the first power semiconductor element; and a temperature estimation unit that estimates a temperature of the first power semiconductor element based on a characteristic of the change of the current of the first power semiconductor element with respect to a change of the voltage applied to the first power semiconductor element.