An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.

Advanced structures having MOSFET transistors and metal layers are disclosed. In one embodiment, a transistor structure is provided that includes a first transistor layer, a second transistor layer located under the first transistor layer, a first power bus layer located above the first transistor layer, a second power bus layer located under the second transistor layer, and a first interconnect layer located above the first power bus layer.

A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

The invention achieves a lower noise of a sense signal of a FET-type hydrogen sensor. For solving the above problem, one aspect of a sensor system of the invention includes a reference device and a sensor device configured using FETs on a substrate, and further, well potentials of the reference device and the sensor device are electrically isolated from each other.