Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

A chip includes a first die, a second die, a first and a second through-silicon vias, a first protection circuit, and a second protection circuit. The first die has a first operational voltage node and a first reference voltage node. The second die has a second operational voltage node and a second reference voltage node. The first and the second through-silicon vias are configured to couple the first die and the second die. The first protection circuit is coupled between the first operational voltage node and the first through-silicon via. The second protection circuit is coupled between the first reference voltage node and the second through-silicon via. The first through-silicon via is further coupled to the second reference voltage node or the second operational voltage node. The second through-silicon via is further coupled to the first reference voltage node or the first operational voltage node.

A chip includes a first die, a second die, a first and a second through-silicon vias, a first protection circuit, and a second protection circuit. The first die has a first operational voltage node and a first reference voltage node. The second die has a second operational voltage node and a second reference voltage node. The first and the second through-silicon vias are configured to couple the first die and the second die. The first protection circuit is coupled between the first operational voltage node and the first through-silicon via. The second protection circuit is coupled between the first reference voltage node and the second through-silicon via. The first through-silicon via is further coupled to the second reference voltage node or the second operational voltage node. The second through-silicon via is further coupled to the first reference voltage node or the first operational voltage node.

Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.

A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.

A semiconductor device having a transistor with fin structure includes a channel layer that is disposed over a substrate and is connected to the substrate via a semiconductor layer, a source layer that is disposed on a first side surface of the channel layer over the substrate and is separated from the substrate via a first insulating layer, a drain layer that is disposed on a second side surface of the channel layer opposite to the first side surface over the substrate and is separated from the substrate via a second insulating layer, and a gate electrode including a first portion disposed over the channel layer and a second portion which is disposed between the substrate and the channel layer and whose third side surface or fourth side surface faces the semiconductor layer.

A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.