Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Example implementations can include a device with a core including a first dielectric material, the core having a mesa structure, a first layer disposed over opposite faces of the mesa structure of the core, the first layer including a metal material, and a second layer disposed over the mesa structure of the core and the first layer, the second layer including a two-dimensional material. Example implementations can include a method of manufacturing a stackable semiconductor device with a two-dimensional material layer, by depositing, over a substrate, a base layer including a first dielectric material, forming, on the base layer, at least one core having a mesa structure, forming sidewalls on opposite vertical surfaces of the mesa structure of the core, depositing, over the core and the sidewalls, a semiconductor layer including a two-dimensional material, and encapsulating the core, the sidewalls, and the semiconductor layer.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

A transistor includes a gate structure, a spacer laterally surrounding the gate structure. a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, and a source/drain contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer.

An ambipolar, gate all around, semiconductor-based transistor includes a substrate, a first-type channel structure located on the substrate, the first-type channel structure having a gate region, a source region, and a drain region, a second-type material located on all sides of the gate region of the first-type channel structure, but not on the source region and the drain region, a dielectric material fully surrounding the second-type material on all the external surface of the gate region, a gate electrode located on the dielectric material, a source electrode located on the source region, and a drain electrode located on the drain region. The first-type is one of p- or n-type and the second type is another of the p- or n-type.

A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, a p-type semiconductor layer, a first passivation layer, a first electrode metal layer, and a second electrode metal layer. The n-type semiconductor layer is disposed above the substrate, and comprises a metal oxide material. The p-type semiconductor layer is disposed above the substrate, and comprises an organic semiconductor material. The first passivation layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole. The first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.

A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, a p-type semiconductor layer, a first passivation layer, a first electrode metal layer, and a second electrode metal layer. The n-type semiconductor layer is disposed above the substrate, and comprises a metal oxide material. The p-type semiconductor layer is disposed above the substrate, and comprises an organic semiconductor material. The first passivation layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole. The first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.