Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

The invention relates to a silicon-based multifunction substrate. The silicon-based multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.

The invention relates to a silicon-based multifunction substrate. The silicon-based multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.

Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.

Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.

The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.

The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.

The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

According to example embodiments, an integrated circuit includes a continuous active region extending in a first direction, a tie gate electrode extending in a second direction crossing the first direction on the continuous active region, a source/drain region provided adjacent the tie gate electrode, a tie gate contact extending in a third direction perpendicular to the first direction and the second direction on the continuous active region and connected to the tie gate electrode, a source/drain contact extending in the third direction and connected to the source/drain region, and a wiring pattern connected to each of the tie gate contact and the source/drain contact and extending in a horizontal direction. A positive supply power is applied to the wiring pattern.