Provided is a semiconductor package having a package housing in an engraved surface form and a method of manufacturing the same, wherein the semiconductor package includes: at least one substrate on which at least one semiconductor chip is installed; at least one terminal lead electrically connected to the substrates; electrical connectors for connecting the semiconductor chips to the substrates or the terminal leads; a package housing covering the semiconductor chips, the electrical connectors, and the at least one substrate; at least one stopper which is formed of a material same as that of the package housing, is higher by a certain height than exposed surfaces of the substrates, is disposed on the exposed surfaces of the substrates, or covers at least a part of the exposed surfaces; and at least one heat sink transmitting heat from the semiconductor chips and radiating heat, wherein the at least a part of the exposed surfaces of the at least one substrate is formed on the upper surface, the lower surface, or the upper and lower surfaces of the package housing and the exposed surfaces of the at least one substrate are joined to the heat sinks by using heat transfer connectors interposed therebetween. Accordingly, the full thickness of the heat transfer connectors may be uniformly maintained.

A low parasitic inductance power module featuring staggered interleaving conductive members, including: at least one base extending in a length direction; a substrate on which at least one input bus bar and at least one output bus bar are provided; a first unit including a first circuit base portion disposed on the base in a width direction, a plurality of first power devices being disposed on the first circuit base portion, each first power device having a first current input end and a first current output end which are parallel connected, the first current input end or the first current output end being conducted to the first circuit base portion; and a second unit. The units are serially-connected to the bus bars via input conductive members and output conductive members arrayed in a staggered interleaving mode, whereby to create individual inductances counteracting with each other, reducing overall parasitic inductance.

Microwave packaging uses signal vias and interposers, such as metal lead frame interposers. For example, the microwave circuit die includes signal vias that electrically connect the top side and the bottom side of the die. Microwave signal circuitry on the die have signal paths that are electrically connected to the top side of the signal vias. The microwave signal circuitry typically may have an operating frequency of 300 MHz or faster. The bottom side of the signal vias are electrically connected to corresponding areas on the top side of the interposer. The bottom side of the die may also include a ground plane, with ground vias that electrically connect the top side of the die to the ground plane.

A semiconductor device of an embodiment includes: a wiring board; a semiconductor chip mounted on the wiring board; and a resin-containing layer bonded on the wiring board so as to fix the semiconductor chip to the wiring board. The resin-containing layer contains a resin-containing material having a breaking strength of 15 MPa or more at 125° C.

In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including a first leadframe portion including a first plurality of signal leads, and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include one or more semiconductor die that are electrically coupled with the substrate and the leadframe portions.

In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

A 3-D package structure for isolated power module is discussed. The package structure has metal trace in a support layer (e.g. a substrate board), which is covered by two magnetic films from both sides, thus an effective transformer is formed. An IC die which contains a voltage regulator is stacked above the support layer, which significantly reduces the package size.

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

A method for producing a power semiconductor system includes packaging a power device in plastic to form a power semiconductor component, forming a first heat dissipation face on a surface of the power semiconductor component; heating a first material between a first heat sink and the first heat dissipation face; and cooling the first material on the first heat dissipation face to connect the power semiconductor component and the first heat sink.

An intelligent power module, which includes: a lead frame; a plurality of signal processing chips, disposed on the lead frame; at least one bridge die, configured to operably transmit signals among the signal processing chips; and a package structure, encapsulating the lead frame, the signal processing chips and the bridge die.