A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.

A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.

An anti-fuse element includes a first electrode, an insulating layer disposed on the first electrode, and a second electrode disposed on the insulating layer. The insulating layer includes a first region and a second region, with a thickness of the first region being smaller than a thickness of the second region. An outer edge of the second electrode is located inward of an outer edge of the insulating layer in a top view.

The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

A method of constructing a superconducting switch includes depositing a thin sacrificial layer on top of a substrate. The sacrificial layer is patterned to remove portions of the sacrificial layer except at a first portion of the substrate. A superconducting metal layer is patterned on top of the substrate and on top of the sacrificial layer. The superconducting metal layer is patterned to form a superconducting metal line over the sacrificial layer. The patterned sacrificial layer is etched from under the superconducting metal line to release the metal line from the substrate.

An array substrate, a fabricating method thereof, and a related display device are provided. The method for forming an array substrate can comprises: forming a plurality of signal lines over a base substrate; forming a conductive line over the base substrate, the conductive line connecting at least two of the plurality of signal lines; forming an insulating layer over the base substrate, the plurality of signal lines, and the conductive line; forming a via hole through the insulating layer at a position over the conductive line and between the at least two of the plurality of signal lines; and removing a portion of the conductive line through the via hole to disconnect the conductive line.

A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.

An array substrate, a fabricating method thereof, and a related display device are provided. The method for forming an array substrate can comprises: forming a plurality of signal lines over a base substrate; forming a conductive line over the base substrate, the conductive line connecting at least two of the plurality of signal lines; forming an insulating layer over the base substrate, the plurality of signal lines, and the conductive line; forming a via hole through the insulating layer at a position over the conductive line and between the at least two of the plurality of signal lines; and removing a portion of the conductive line through the via hole to disconnect the conductive line.

An array substrate, a fabricating method thereof, and a related display device are provided. The method for forming an array substrate can comprises: forming a plurality of signal lines over a base substrate; forming a conductive line over the base substrate, the conductive line connecting at least two of the plurality of signal lines; forming an insulating layer over the base substrate, the plurality of signal lines, and the conductive line; forming a via hole through the insulating layer at a position over the conductive line and between the at least two of the plurality of signal lines; and removing a portion of the conductive line through the via hole to disconnect the conductive line.

A method of constructing a superconducting switch includes depositing a thin sacrificial layer on top of a substrate. The sacrificial layer is patterned to remove portions of the sacrificial layer except at a first portion of the substrate. A superconducting metal layer is patterned on top of the substrate and on top of the sacrificial layer. The superconducting metal layer is patterned to form a superconducting metal line over the sacrificial layer. The patterned sacrificial layer is etched from under the superconducting metal line to release the metal line from the substrate.