A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.

A semiconductor device includes a high-voltage semiconductor transistor chip having a front side and a backside. A low-voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further includes a dielectric inorganic substrate having a first side and a second side opposite the first side. A pattern of first metal structures runs through the dielectric inorganic substrate and is connected to the low-voltage load electrode. At least one second metal structure runs through the dielectric inorganic substrate and is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 μm.

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

A semiconductor structure includes a semiconductor feature, a protection layer and a polymeric layer. The semiconductor feature includes a passivation layer, an interconnecting structure disposed on the passivation layer, and a dielectric layer disposed on the passivation layer and the interconnecting structure. The protection layer is disposed on the dielectric layer, and is oxide-and-nitride based. The polymeric layer is disposed on the protection layer, and is separated from the interconnecting structure by the protection layer. A method of making a semiconductor structure is also provided.

A semiconductor structure includes: a base; a first conductive layer, having a portion located within the base and a remaining portion protruding above the base; a barrier layer on the base and at least on a sidewall of the first conductive layer protruding from the base; a dielectric layer on the barrier layer; and a second conductive layer penetrating the dielectric layer and the barrier layer, in contact with the sidewall of the barrier layer, and in contact with at least a portion of the upper surface of the first conductive layer.

Disclosed semiconductor device manufacturing processes improve the flatness of a passivation layer deposited above a redistribution layer (RDL). When a thin passivation layer is deposited above the RDL, its top surface tends to become very uneven due to the large gaps that typically form over the etched portions of the RDL, particularly when the RDL is disposed over an underlying super high density metal-insulator-metal (MIM) capacitor. In order to reduce the incidence of stress concentration areas on the uneven surface, a thicker passivation layer is instead deposited to minimize gap formation therein, and a chemical mechanical planarization (CMP) process is then performed to further smooth the top surface thereof. Reduction of the stress in this manner reduces the incidence of cracking of the underlying MIM, which improves the overall pass rates of semiconductor devices so manufactured.

A semiconductor device includes a substrate having an active region, a first insulating layer on the substrate, a second insulating layer on the first insulating layer, an etch stop layer between the first insulating layer and the second insulating layer, a via contact in the first insulating layer and electrically connected to the active region, an interconnection electrode in the second insulating layer and electrically connected to the via contact, a conductive barrier layer on a side surface and a lower surface of the interconnection electrode and having an extension portion extending to a partial region of a side surface of the via contact, and a side insulating layer on a side region of the via contact below the extension portion of the conductive barrier layer, the side insulating layer including the same material as a material of the etch stop layer.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.