According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.

According to one embodiment, a semiconductor device includes a first circuit, a first terminal, a second terminal, a conductor and a first switch element serially coupled between the first terminal and the second terminal, wherein the first circuit is configured to turn the first switch element to an OFF state when a first condition is satisfied, and the conductor is configured to physically break when a second condition is satisfied.

The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

The embodiments provide a detection circuit and a detection method. The detection circuit includes an ESD protection device, a first fuse and a transistor. A first terminal of the ESD protection device is connected to a first terminal of the first fuse, and a connection terminal of the ESD protection device and the first fuse serves as a first test terminal; a second terminal of the first fuse is connected to a gate electrode of the transistor, and a connection terminal of the first fuse and the transistor serves as a second test terminal; and a second terminal of the ESD protection device is connected to at least one of a source electrode, drain electrode or substrate of the transistor, and a connection terminal of the ESD protection device and the transistor serves as a third test terminal.

Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

A transistor is disclosed that includes a substrate, an active layer, a gate electrode, a first electrode, a second electrode, and a first connection electrode. The active includes a first region, a second region, and a channel region between the first region and the second region. The gate electrode is disposed on the active layer and overlaps the channel region. The first electrode is disposed on the substrate and electrically connects to the first region. The second electrode is disposed on the substrate and electrically connects to the second region. The first connection electrode is disposed on the substrate and electrically connects the gate electrode and the second electrode.

Provided is a semiconductor device, including an insulating layer, a transistor located on the insulating layer, and a conductive structure, in which the transistor includes: a source, a channel and a drain arranged in parallel, as well as a gate dielectric layer and a gate structure, in which the gate dielectric layer is located between the gate structure and the channel; the conductive structure covers one sidewall of the channel and is used for grounding; the gate structure is disposed around the other three sidewalls of the channel; and the gate structure and the conductive structure are isolated from each other.

A wafer includes a substrate that includes a channel layer, a first active region, a second active region, and a saw street region between the first active region and the second active region. The wafer includes a first device formed on the substrate in the first active region. The first device includes a first portion of the channel layer. The wafer includes a second device formed on the substrate in the second active region. The second device includes a second portion of the channel layer. The wafer includes a conductive channel between the first active region and the second active region. The conductive channel is in the saw street of the wafer and includes a third portion of the channel layer.

Two approaches for on-chip ESD detection include variable dielectric width capacitor, and vertical metal-oxide-semiconductor (MOS) capacitor MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate ready breakdown of a thin dielectric between the metal plates. The vertical MOSCAP array is composed of a capacitor array connected in series. Both approaches are incorporated in an example 22 nm fully depleted silicon-on-insulator. Vertical MOSCAP arrays detect ESD events starting from about 6 V with about 6 V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from about 40 V and above.

A display device is provided. The display device includes a panel. The panel includes a display region and a non-display region and has a normal direction in which the non-display region is adjacent to the display region. The non-display region includes a first conductive line and a second conductive line. A common voltage is applied to the first conductive line. The second conductive line is at least partially overlapped with the first conductive line. There is a distance between the first conductive line and the second conductive line in the normal direction. The distance is greater than or equal to 3500 Å, and less than or equal to 4500 Å.