A semiconductor storage device includes a circuit region formed on a semiconductor substrate, and a guard ring region spaced from one side of the circuit region by a predetermined distance. The guard ring region extends in a first direction, the first direction being a direction in which the one side of the circuit region extends, includes a guard ring line, an element isolation region, a first defect trapping layer, a second defect trapping layer. The first defect trapping layer extends from a boundary location between the circuit region and the element isolation region to a location spaced from a boundary location between the element isolation region and the guard ring line by an offset distance toward the element isolation region in the second direction.

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

The present disclosure relates to a display substrate, a method for driving the same, and a display panel. The display substrate includes a base substrate as well as gate lines, data lines and a gate driver on the base substrate, the gate line being connected to the gate driver, and electrostatic rings and control components corresponding to at least one gate line are further disposed on the base substrate, each of the gate lines being connected to the electrostatic ring by a corresponding control component. The electrostatic ring is configured to load a control voltage to turn on the corresponding control component after the display panel is turned off, and the corresponding control component is configured to be turned on to change a voltage on the gate line into a turn-on voltage after the display panel is turned off.

Disclosed are a display substrate and a display device. The display substrate includes: a base substrate; a plurality of gate lines and a plurality of data lines on the base substrate that intersect to surround a plurality of pixels; at least one thin film transistor on the base substrate and located in each pixel, each thin film transistor including a gate electrode, a first electrode and a second electrode; a storage capacitor on the base substrate and located in each pixel, the storage capacitor including a first capacitor electrode and a second capacitor electrode that are disposed oppositely and located in the same layer, wherein the first capacitor electrode comprises at least an electrode body; and a tip structure, the tip structure and the first capacitor electrode being located in the same layer, and the tip structure including a first tip sub-structure and a second tip sub-structure.

A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.

A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

A biological-electrode protection module is a monolithic component including a capacitor and a voltage-limiting component integrated in a common substrate. The capacitor component is connected in the series path between the input and output terminals. The voltage-limiting component is connected between ground and a node in the series path. The voltage-limiting component has a low breakdown voltage no greater than 6 volts and may be a biphasic device operating in the punch-through mode. Moreover, the protection module is connected to or integrated with a set of biological electrodes at a distance no greater than 1 cm. The capacitor may be a 3D capacitor, and common fabrication processes may be used in forming the voltage-limiting component and the capacitor. A JFET may be integrated in the same substrate so that an electrical signal output from the monolithic protection device is already pre-amplified.

This application provides a chip apparatus, including a die, a first bond pad, a second bond pad, and a first solder pad. The first bond pad and the second bond pad are disposed on an upper surface of the die. A first power module and a second power module are disposed in the die. The first power module is coupled to the first bond pad. The second power module is coupled to the second bond pad. The first solder pad is separately coupled to an external power supply of the chip apparatus, the first bond pad, and the second bond pad. According to the foregoing technical solution, isolation between different power modules is improved, and noise transmitted on a power supply path can be better filtered out. This improves power supply noise performance of the chip apparatus.

According to one embodiment, a display device includes first semiconductor layers crossing a first scanning line in a non-display area, the first semiconductor layers being a in number, second semiconductor layers crossing a second scanning line in the non-display area, the second semiconductor layers being b in number, and an insulating film disposed between the first and second semiconductor layers and the first and second scanning lines, wherein a and b are integers greater than or equal to 2, and a is different from b, and the first and second semiconductor layers are both entirely covered with the insulating film.

An integrated circuit with a fault reporting structure. The integrated circuit has at least one power MOSFET having a plurality of MOSFET cells with each MOSFET cell having a drain metal and a source metal, and the integrated circuit has a power MOSFET area for routing the drain metals and the source metals of the plurality of MOSFET cells. The fault reporting structure has a metal net routed in the power MOSFET area or in an area above or below the power MOSFET area.