The present disclosure provides a light-emitting substrate, a backlight and a display device. The light-emitting substrate includes a light-emitting region and a peripheral region surrounding the light-emitting region. The peripheral region includes a first area, the first area is located between a first side of the light-emitting substrate and the light-emitting region, the light-emitting substrate further includes a first signal line, the first signal line includes at least one selected from a group consisting of a first portion and a second portion, the first portion of the first signal line extends along a first direction in the first area, the second portion of the first signal line extends into the light-emitting region, the first portion and the second portion of the first signal line are connected when the first signal line includes the first portion and the second portion.

The present disclosure provides an electronic device including a substrate, a common electrode, and a plurality of pixels. The common electrode is disposed on the substrate. The pixels are disposed on the substrate, and at least one of the pixels includes a thin film transistor, a first electrode, a second electrode, and an auxiliary electrode. The first electrode is electrically connected to the thin film transistor. The auxiliary electrode is electrically connected to the common electrode and electrically isolated from the first electrode, and the first electrode and the auxiliary electrode have a minimum distance less than a minimum distance between the first electrode and the common electrode.

The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.

A semiconductor device includes a protection element configured by a MOSFET, and the protection element has a multilayer metal wiring structure. The multilayer metal wiring structure includes drain connection wirings connected to drain regions of the MOSFET and source connection wirings connected to source regions of the MOSFET. In a part of a layer of the multilayer metal wiring structure where both the drain connection wirings and the source connection wirings are present, only either the drain connection wirings or the source connection wirings are laid out in a grained pattern.

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

The present invention relates to a semiconductor electrostatic protection device, including: a substrate, a deep well region of a first conductivity type being formed in the substrate; a first diode, an anode of the first diode being connected to a first voltage, and a cathode of the first diode being connected to an input/output terminal; and a second diode, an anode of the second diode being connected to the input/output terminal, and a cathode of the second diode being connected to a second voltage; the first diode and the second diode being located in the deep well region of the first conductivity type.

A detection device comprises a substrate, a terminal part provided on the substrate and having a plurality of terminals, a first protection circuit unit provided on the substrate and having a plurality of first protection circuits, a selector unit provided on the substrate and having a plurality of selectors, a second protection circuit unit provided on the substrate and having a plurality of second protection circuits and a sensor unit provided on the substrate and having a plurality of sensors. The first protection circuit unit is provided between the terminal unit and the selector unit, and the second protection circuit unit is provided between selector unit and the sensor unit.

Disclosed are a surge protection device and a chip constituted thereby, and a communication terminal. The surge protection device comprises an input pad and an output pad. The input pad is connected to a power supply voltage, and the output pad is connected to a ground wire. NMOS transistor groups are provided between the input pad and the output pad. The NMOS transistor groups are connected to the input pad and the output pad respectively by means of metal wires. The structures of the metal wires between the NMOS transistor groups and the input pad and the output pad respectively and/or the structures of the NMOS transistor groups are changed to reduce or cancel non-uniform turn-on of the NMOS transistor groups caused by metal wires having different lengths from the NMOS transistor groups to the input pad and the output pad respectively along a power supply voltage wire direction.

A display device may include a substrate, a pixel, a transistor, a data line, a connection line, a pad, and an electrostatic discharge protection circuit. The substrate may include a display area and a pad area. The pad area may overlap the display area. The pixel may be supported by the display area and may include a pixel electrode. The data line may be electrically connected through the transistor to the pixel electrode. The connection line may be supported by the display area and may be electrically connected through the data line to the transistor. The pad may be supported by the pad area and may be electrically connected through the connection line to the data line. The display area and the pad area may be positioned between the connection line and the pad. The electrostatic discharge protection circuit may be electrically connected to the connection line.