A transistor is disclosed that includes a substrate, an active layer, a gate electrode, a first electrode, a second electrode, and a first connection electrode. The active includes a first region, a second region, and a channel region between the first region and the second region. The gate electrode is disposed on the active layer and overlaps the channel region. The first electrode is disposed on the substrate and electrically connects to the first region. The second electrode is disposed on the substrate and electrically connects to the second region. The first connection electrode is disposed on the substrate and electrically connects the gate electrode and the second electrode.

The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

A gate driver on array (GOA) circuit and a display panel including the same are provided. The GOA circuit includes: a GOA drive signal line including a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line.

A semiconductor storage device includes a circuit region formed on a semiconductor substrate, and a guard ring region spaced from one side of the circuit region by a predetermined distance. The guard ring region extends in a first direction, the first direction being a direction in which the one side of the circuit region extends, includes a guard ring line, an element isolation region, a first defect trapping layer, a second defect trapping layer. The first defect trapping layer extends from a boundary location between the circuit region and the element isolation region to a location spaced from a boundary location between the element isolation region and the guard ring line by an offset distance toward the element isolation region in the second direction.

A display substrate and a display device are provided. The display substrate includes a base substrate, the base substrate includes a display region and a periphery region; a plurality of data signal transmission lines, a plurality of signal output pads, a plurality of signal input pads, and a plurality of test pads are located in the periphery region; a plurality of sub-pixels and a plurality of data lines are located in the display region; the plurality of data signal transmission lines are electrically connected with at least part of the plurality of data lines; the periphery region is provided with a plurality of electrostatic release elements located between the plurality of signal output pads and the plurality of test pads, each electrostatic release element is electrically connected with one data signal transmission line and is configured to release static electricity on the data signal transmission line.

The present disclosure provides an electro-static discharge protection device for a semiconductor, including: a substrate of a first conductive type, a deep well region of a second conductive type being formed in the substrate of the first conductive type; first diodes, located in the deep well region of the second conductive type, anodes of the first diodes being connected to a first voltage through a plurality of first metal lines; second diodes, located in the deep well region of the second conductive type; a first pad, connected to the anodes of the first diodes through the plurality of first metal lines, and connected to the first voltage; a second pad, connected to cathodes of the second diodes through a plurality of second metal lines, and connected to a second voltage.

An ESD protection circuit including a TFT arranged between a to-be-protected signal line and a discharging line is provided, wherein a length direction of a channel of the TFT is parallel to an extension direction of the to-be-protected signal line. A display panel and a display device are also provided.

An electrostatic protection circuit and a manufacturing method thereof, an array substrate, and a display device are provided. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line.

A semiconductor device includes, for example, an external terminal, an output element, a detecting element configured to detect occurrence of a negative voltage at the external terminal, and an off-circuit configured to forcibly turn off the output element when the detecting element detects occurrence of the negative voltage.