A display device includes a display panel including a plurality of pixels, a first panel pad, and a second panel pad and a circuit board including a first substrate pad and a second substrate pad to apply a first power voltage to the first panel pad and the second panel. The display panel further includes a first power line pattern connected to the second substrate pad to apply the first power voltage to the pixels and a second power line pattern connected to the first substrate pad. The circuit board includes a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad, a substrate power pattern electrically connected to the first substrate pad, a ground pattern receiving a ground voltage, and a second electrostatic discharge protection circuit connected between the substrate power pattern and the ground pattern.

A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

A semiconductor structure is provided having improved electrostatic contact close to the dielectric pillar that separates a first device region from a second device region. The semiconductor structure includes a dielectric pillar located between a first vertical nanosheet stack of suspended semiconductor channel material nanosheets and a second vertical nanosheet stack of suspended semiconductor channel material nanosheets. Horizontal dielectric bridge structures can be located in the first and second device regions. The horizontal bridge structures connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar. A dielectric spacer structure can laterally surround a lower portion of the dielectric pillar and be present in a semiconductor substrate. In some embodiments, the horizontal dielectric bridge structures can be omitted.

A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming control circuitry of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth and fifth metal layers above second level; a global power distribution grid includes fifth metal, and local power distribution grid includes the second metal layer, where the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.

The present disclosure provides an electronic device including a substrate, a common electrode, and a plurality of pixels. The common electrode is disposed on the substrate. The pixels are disposed on the substrate, and at least one of the pixels includes a thin film transistor, a first electrode, a second electrode, and an auxiliary electrode. The first electrode is electrically connected to the thin film transistor. The auxiliary electrode is electrically connected to the common electrode and electrically isolated from the first electrode, and the first electrode and the auxiliary electrode have a minimum distance less than a minimum distance between the first electrode and the common electrode.

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

An anti-corrosion circuit, an array substrate and an electronic device are provided. The array substrate includes: source signal lines, provided in the display area, extending along a first direction and arranged sequentially along a second direction; a first power bus line, provided in the peripheral area and including a main body portion extending along the second direction; an electrostatic discharge protection circuit, provided on a side of the main body portion away from the display area and electrically connected to the source signal lines, and including first sub-signal lines and second sub-signal lines. The first sub-signal lines and the second sub-signal lines extend along the second direction and are alternately arranged along the first direction, and the main body portion is adjacent to one first sub-signal line, and electrical property of the first power bus line is the same as electrical property of the one first sub-signal line.

The present invention relates to a semiconductor electrostatic protection device, including: a substrate, a deep well region of a first conductivity type being formed in the substrate; a first diode, an anode of the first diode being connected to a first voltage, and a cathode of the first diode being connected to an input/output terminal; and a second diode, an anode of the second diode being connected to the input/output terminal, and a cathode of the second diode being connected to a second voltage; the first diode and the second diode being located in the deep well region of the first conductivity type.

The disclosure relates to a display substrate, including: a base substrate including a display area and a peripheral area surrounding the display area; a first crack detection line located in the peripheral area and surrounding the display area; a second crack detection line located in the peripheral area and surrounding the display area; at least one first electrostatic discharge circuit located in the peripheral area, each including at least one first thin film transistor, the at least one first thin film transistor including a first gate; and at least one second electrostatic discharge circuit located in the peripheral area and electrically connected to the second crack detection line, each including at least one second thin film transistor, the at least one second thin film transistor including a second gate, wherein the second gate is electrically connected to the first gate.

A detection device comprises a substrate, a terminal part provided on the substrate and having a plurality of terminals, a first protection circuit unit provided on the substrate and having a plurality of first protection circuits, a selector unit provided on the substrate and having a plurality of selectors, a second protection circuit unit provided on the substrate and having a plurality of second protection circuits and a sensor unit provided on the substrate and having a plurality of sensors. The first protection circuit unit is provided between the terminal unit and the selector unit, and the second protection circuit unit is provided between selector unit and the sensor unit.