To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

An anti-static metal oxide semiconductor field effect transistor structure includes an anti-static body structure and a slave metal oxide semiconductor field effect transistor, the anti-static body structure includes: a main metal oxide semiconductor field effect transistor; a first silicon controlled rectifier, an anode thereof being connected to a drain of the main metal oxide semiconductor field effect transistor, a cathode and a control electrode thereof being connected to a source of the main metal oxide semiconductor field effect transistor; and a second silicon controlled rectifier, an anode thereof being connected to the drain of the main metal oxide semiconductor field effect transistor, a cathode thereof being connected to a gate of the main metal oxide semiconductor field effect transistor, a control electrode thereof being connected to the source or the gate of the main metal oxide semiconductor field effect transistor.

An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

Provided is an n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device including: an n.sup.+ drain layer; a parallel pn layer including n.sup.− drift and p pillar layers joined alternately; a composite layer including a p base layer and an n.sup.+ source layer, the n.sup.+ drain layer, the parallel pn layer, and the composite layer being provided in order; a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the n.sup.+ source layer; and a high-resistance layer provided between the p pillar layer and the p base layer, the p pillar layer having an impurity concentration lower than that of the n.sup.− drift layer.

This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.

In some embodiments, a semiconductor chip can include a substrate, an active wide-bandgap device implemented on the substrate, and a reference wide-bandgap device implemented on the substrate. The reference wide-bandgap device can be configured to provide a response to a condition that also affects the active wide-bandgap device. Such a semiconductor chip can be included in an architecture that allows operation of the active wide-bandgap device based on the response provided by the reference wide-bandgap device.

A semiconductor device includes a first transistor, a second transistor, a third electrode, and a control layer. The first transistor includes a first region of a semiconductor layer, a first electrode, and a first gate electrode. The first electrode is electrically connected with the first region. The first gate electrode is located in the first region. The second transistor includes a second region of the semiconductor layer, a second gate electrode, and a second electrode. The second region is next to the first region. The second gate electrode is located in the second region. The second electrode is electrically connected with the second region. The third electrode is electrically connected with the first and second transistors. The control layer has a smaller linear expansion coefficient than the third electrode.

This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.

The invention solves the problem of depressed SOA of a bipolar junction transistor (BJT) when operated in an open base configuration by integrating in the same semiconductor chip a switchable short between the base and the emitter of the BJT. The switchable short switches between a high resistive value when the collector voltage of the BJT is lower than the base voltage. and a lower resistive value when the collector voltage is higher than the voltage base to effectively lower the BJT current gain (h.sub.FE). The switchable short in one implementation of the invention is in the form of a MOSFET with its gate connected to the BJT collector. The invention further teaches disposing in the integrated circuit chip a junction diode with a breakdown voltage lower than the BVCBO of the BJT. The addition of the junction diode provides a measure of maintaining the effectiveness of the MOSFET as switchable short at a reduced size.