Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage can be applied to the back gate of the FET.

Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a semiconductor region, an insulative layer disposed above the semiconductor region, and a first non-insulative region disposed above the insulative layer. In certain aspects, a second non-insulative region is disposed adjacent to the semiconductor region, and a control region is disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region. In certain aspects, the first non-insulative region is disposed above a first portion of the semiconductor region and a second portion of the semiconductor region, and the first portion and the second portion of the semiconductor region are disposed adjacent to a first side and a second side, respectively, of the control region or the second non-insulative region.

The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

A FinMosVar (fin metal oxide semiconductor (MOS) varactor) has an improved number of fins. The number of fins are determined based on a measured or calculated gate resistance of the FinMosVar and a measured or calculated capacitance of the FinMosVar. The number of fins is less than twenty (20) fins. The FinMosVar also includes a source region, a drain region and a channel region. The drain region has a same type of doping as the source region. The channel region has the same type of doping as the source region.

The present disclosure relates to semiconductor structures and, more particularly, to a back-gate controlled varactor and methods of use and manufacture. The varactor includes: a plurality of transistors arranged in parallel; a voltage controlled node coupled to back-gates of the plurality of transistors; and a biasing voltage node coupled to the source and drain of the plurality of transistors.