A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material may include a positive capacitance material. The capacitor may further include a second insulating material disposed over the first insulating material and between the first insulating material and the second conductive layer. The second insulating material may include a negative capacitance ferroelectric material.

A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage can be applied to the back gate of the FET.

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.

Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes an insulative layer, and a semiconductor region disposed adjacent to a first side of the insulative layer. The semiconductor capacitor also includes a first non-insulative region disposed adjacent to a second side of the insulative layer. In certain aspects, the semiconductor region may include a second non-insulative region, wherein the semiconductor region includes at least two regions having at least one of different doping concentrations or different doping types, and wherein one or more junctions between the at least two regions are disposed above or below the first non-insulative region.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes an insulative layer, and a semiconductor region disposed adjacent to a first side of the insulative layer. The semiconductor capacitor also includes a first non-insulative region disposed adjacent to a second side of the insulative layer. In certain aspects, the semiconductor region may include a second non-insulative region, wherein the semiconductor region includes at least two regions having at least one of different doping concentrations or different doping types, and wherein one or more junctions between the at least two regions are disposed above or below the first non-insulative region.

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Certain aspects of the present disclosure provide a semiconductor variable capacitor based on a buried oxide process. The semiconductor variable capacitor generally includes a first conductive pad coupled to a first non-insulative region and a second conductive pad coupled to a second non-insulative region. The second non-insulative region may be coupled to a semiconductor region. The capacitor may also include a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region. The capacitor also includes an insulator region disposed below the semiconductor region, wherein at least a portion of the first non-insulative region is separated from the second non-insulative region by the insulator region such that the first conductive pad is electrically isolated from the second conductive pad.