A detection device for detecting at least the occurrence and location of occurrence of sensor element signals that are generated by sensor elements, includes an array of detector element circuits each generating a element row output and at least one element column output. The detection device determines, for each row of detector element circuits, at least a first row summation signal corresponding to a sum of the element row outputs of the detector element circuits of this row, and a row address signal indicating that the first row summation signal crosses a threshold. The detection device also determines, for each column of detector element circuits, at least a first column summation signal corresponding to a sum of the element column outputs of the detector element circuits of this column, and a column address signal indicating that the first column summation signal crosses a threshold.

An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.

A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.

A light receiving element including: a semiconductor substrate; a photoelectric conversion unit (PD) in the semiconductor substrate that converts light into electric charges; a first electric charge accumulation unit (MEM) in the semiconductor substrate to which the electric charges are transferred from the photoelectric conversion unit; a first distribution gate on a front surface of the semiconductor substrate that distributes the electric charges from the photoelectric conversion unit to the first electric charge accumulation unit; a second electric charge accumulation unit (MEM) in the semiconductor substrate to which the electric charges are transferred from the photoelectric conversion unit; and a second distribution gate on the front surface of the semiconductor substrate that distributes the electric charges from the photoelectric conversion unit to the second electric charge accumulation unit, in which the first and second distribution gates each have a pair of buried gate portions.

Techniques are described for implementing a split-select-block (split-SEL) complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel physical architecture, such as for reducing noise in low-light application contexts. The split-SEL CIS pixel physical architecture can include a pixel block with one or more photodiodes. Above the photodiodes, there can be: a first oxide diffusion region with a reset block and a gain block disposed thereon; and a second oxide diffusion region with a select block disposed thereon. Below the photodiodes, there can be a third oxide diffusion region with a source follower (SF) block (e.g., a square-gate SF transistor) disposed thereon. A trace can be routed through the set of photodiodes to couple the source of the SF block with the select block. The architecture permits an appreciable increase in the physical gate length and/or other features.

An image sensor may include a substrate including first and second surfaces opposite to each other and including a single crystalline layer, a first epitaxial layer, and a second epitaxial layer sequentially stacked from the second surface. The single crystalline layer and the second epitaxial layer may be doped with first impurities of a first conductivity type. The first epitaxial layer may be doped with second impurities of a second conductivity type. A pixel separation structure extends from the first surface to penetrate at least the second and first epitaxial layers and divides the substrate into a plurality of pixels. A transfer gate electrode extends from the first surface to penetrate the second epitaxial layer. A doping concentration of the first impurities doped in the single crystalline layer may be higher than that in the second epitaxial layer.

A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.

An image sensor is provided. The image sensor includes: a pixel array including a plurality of pixels arranged along rows and columns; and a row driver which drives the plurality of pixels for each of the rows, wherein each of the plurality of pixels includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a plurality of photoelectric conversion elements sharing a floating diffusion area with each other, and a micro lens disposed to overlap the plurality of photoelectric conversion elements, a readout area is defined on the pixel array in accordance with a preset readout mode, and the row driver generates a drive signal for reading out signals provided from a photoelectric conversion element included in the readout area from among the plurality of photoelectric conversion elements, and provides the drive signal to the pixel array.

An imaging apparatus includes a pixel region including a first substrate section and pixels, and a peripheral region including a second substrate section and no pixels. Each of the pixels includes a first electrode; a second electrode; a photoelectric conversion layer that is disposed between the first electrode and the second electrode; and a charge accumulation region disposed in the first substrate section. The pixel region includes first penetrating electrodes that electrically connect the first electrode to the charge accumulation region. The peripheral region includes second penetrating electrodes. An areal density of the first penetrating electrodes that is a ratio of an area of the first penetrating electrodes to an area of the pixel region is different from an areal density of the second penetrating electrodes that is a ratio of an area of the second penetrating electrodes to an area of the peripheral region.

Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in a plurality of time-binning pixels. In some embodiments, an optical component for optical rejection is provided in between a waveguide and the time-binning pixel and configured to block at least some excitation photons in a pulsed light stream from arriving at the photodetection region. In some embodiments, the time-binning pixel does not comprise a time-gated transistor for electronic rejection configured to block a transfer of charge carriers associated with excitation photons in the pulsed light stream.