Patent classifications
H01L27/14609
IMAGING ELEMENT AND IMAGING DEVICE
An imaging element is disclosed that includes: a semiconductor substrate; a multilayer wiring layer; a plurality of structures; and a light reflecting layer. The semiconductor substrate has a first surface as a light incidence surface and a second surface opposite to the first surface. A light receiving section of the semiconductor substrate generates electric charge through photoelectric conversion. The multilayer wiring layer has a plurality of wiring layers and is on the second surface side of the semiconductor substrate. The plurality of structures is in the multilayer wiring layer. The light reflecting layer is in the multilayer wiring layer, and forms a reflective region or a non-reflective region in a region with the interlayer insulating layer interposed in between. The region has none of the structures formed therein. The reflective region and the non-reflective region are substantially symmetrical with respect to the optical center of the pixel.
Solid-state imaging element and solid-state imaging device
A solid-state imaging element including: a photoelectric conversion layer, a first electrode and a second electrode opposed to each other with the photoelectric conversion layer interposed therebetween, a semiconductor layer provided between the first electrode and the photoelectric conversion layer, an accumulation electrode opposed to the photoelectric conversion layer with the semiconductor layer interposed therebetween, an insulating film provided between the accumulation electrode and the semiconductor layer, and a barrier layer provided between the semiconductor layer and the photoelectric conversion layer.
ADJUSTABLE WELL CAPACITY PIXEL FOR SEMICONDUCTOR IMAGING SENSORS
An imaging pixel design is provide with a photo-sensor block structure that facilitates dynamic control of well capacity in the photodiode region (i.e., a “well capacity adjustment (WCA) gate photo-sensor block”). The photodiode region includes a doped well in which photocharge is accumulated responsive to exposure to incident illumination. The capacity of the well corresponds to a well potential. WCA structures (e.g., deep trench regions) form walls at least partially surrounding and capacitively coupling with the doped well, such that biasing of the WCA structures changes the well potential and the corresponding well capacity. As such, the WCA structures can be biased during integration to increase the well potential to a high level for large well capacity, and the WCA structures can be differently biased during photocharge transfer to decrease the well potential to a sufficiently low level that avoids lag and/or other conventional concerns.
Image capturing apparatus, image capturing system, and moving body
An image capturing apparatus includes a plurality of photoelectric conversion elements, a first selection unit, and a second selection unit. Each of the photoelectric conversion elements includes an avalanche diode and a counter. The photoelectric conversion elements have a first photoelectric conversion element and a second photoelectric conversion element. The first selection unit controls the first photoelectric conversion element. The second selection unit controls the second photoelectric conversion element. The first and second selection units are controlled by a first control line and a second control line. In a first mode, the second selection unit controls the second photoelectric conversion element to be brought into a state where no signal is read from the second photoelectric conversion element. In a second mode, the second selection unit controls the second photoelectric conversion element to be brought into a state where a signal is read from the second photoelectric conversion element.
Image sensor
An image sensor includes a first photodiode group, a second photodiode group, a first transfer transistor group, a second transfer transistor group, a floating diffusion region of a substrate in which electric charges generated in the first photodiode group are stored, and a power supply node for applying a power supply voltage to the second photodiode group. A barrier voltage is applied to at least one transfer transistor of the second transfer transistor group. The power supply voltage allows electric charges, generated in the second photodiode group, to migrate to the power supply node, and the barrier voltage forms a potential barrier between the second photodiode group and the floating diffusion region.
Light detection devices with protective liner and methods related to same
Light detection devices and related methods are provided. The devices may comprise a reaction structure for containing a reaction solution with a relatively high or low pH and a plurality of reaction sites that generate light emissions. The devices may comprise a device base comprising a plurality of light sensors, device circuitry coupled to the light sensors, and a plurality of light guides that block excitation light but permit the light emissions to pass to a light sensor. The device base may also include a shield layer extending about each light guide between each light guide and the device circuitry, and a protection layer that is chemically inert with respect to the reaction solution extending about each light guide between each light guide and the shield layer. The protection layer prevents reaction solution that passes through the reaction structure and the light guide from interacting with the device circuitry.
Imaging device
An exemplary imaging device according to the present disclosure includes: an imaging region including a plurality of pixels; a peripheral region located outside of the imaging region; and a blockade region located between the imaging region and the peripheral region Each of the plurality of pixels includes a photoelectric conversion layer, a pixel electrode to collect a charge generated in the photoelectric conversion layer, and a first doped region electrically connected to the pixel electrode. In the peripheral region, a circuit to drive the plurality of pixels is provided. The blockade region includes a second doped region of a first conductivity type located between the imaging region and the peripheral region and a plurality of first contact plugs connected to the second doped region.
Imaging sensor and pixel structure for simultaneous imaging and energy harvesting
An energy harvesting imaging sensor includes an array of pixel structures each formed from a semiconductor having a photodiode overlying a photovoltaic diode. The photodiode and photovoltaic diode are implemented as a vertically stacked P+/N.sub.WELL/P.sub.SUB junction. This structure enables simultaneous imaging and energy harvesting by generating charge in the photodiode that is indicative of light impinging on the photodiode and simultaneously generating charge from the light in the photovoltaic diode located underneath the photodiode.
Solid-state imaging element and electronic device
To provide a solid-state imaging element capable of further improving reliability. Provided is a solid-state imaging element including at least a first photoelectric conversion section, and a semiconductor substrate in which a second photoelectric conversion section is formed, in this order from a light incidence side, in which the first photoelectric conversion section includes at least a first electrode, a photoelectric conversion layer, a first oxide semiconductor layer, a second oxide semiconductor layer, and a second electrode in this order, and a film density of the first oxide semiconductor layer is higher than a film density of the second oxide semiconductor layer.
IMAGE SENSING DEVICE
An image sensing device includes a photoelectric element configured to generate an electric charge in response to light; first and second floating diffusions configured to store the electric charge; a transfer gate having a first end connected to the photoelectric element and a second end connected to the first floating diffusion; a reset transistor configured to reset voltages of the first and second floating diffusions based on a reset signal; a first dual conversion gain (DCG) transistor having a first end connected to the first floating diffusion and a second end connected to the second floating diffusion; first and second pixel circuits configured to generate first and second output voltages based on the first and second floating diffusions; and first and second analog to digital converters configured to receive the first and second output voltages and convert them to first and second digital signals.