Patent classifications
H01L27/14638
IMAGE SENSOR WITH A CONTROL CIRCUIT
An image sensor includes an array of pixels inside and on top of a substrate. A control circuit is configured to apply voltage potentials to the substrate. During a first phase, the control circuit applies a ground potential to the substrate. During a second phase, the control circuit applies a potential positive with respect to the ground potential to the substrate.
IMAGE SENSOR
An image sensor includes a pixel array including first pixels and second pixels, each of the first and second pixels including photodiodes, a sampling circuit detecting a reset voltage and a pixel voltage from the first and second pixels and generating an analog signal, an analog-to-digital converter image data from the analog signal, and a signal processing circuit generating an image using the image data. Each of the first pixels includes a first conductivity-type well separating the photodiodes and having impurities of a first conductivity-type. The photodiodes have impurities of a second conductivity-type different from the first conductivity-type. Each of the second pixels includes a second conductivity-type well separating the photodiodes and having impurities of the second conductivity-type different from the first conductivity-type. A potential level of the second conductivity-type well is higher than a potential level of the first conductivity-type well.
Back side illuminated image sensor with reduced sidewall-induced leakage
Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
Image sensor package
An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.
Imaging element
An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
Image sensor with light blocking layer
An image sensor may include a substrate having a first surface and a second surface on opposite sides, a first transistor having a first gate disposed on the first surface, a photoelectric conversion layer which generates photocharges from light incident in a first direction, a second transistor having a transistor structure disposed between the first surface and the photoelectric conversion layer and spaced from the photoelectric conversion layer, and includes a semiconductor layer composed of a metal oxide semiconductor material. The semiconductor layer may have a third surface facing the first direction and a fourth surface opposite the third surface, with a second gate disposed on the semiconductor layer. The semiconductor layer may be connected to the first gate. A light blocking layer may be disposed between the third surface and the photoelectric conversion layer, and spaced from the photoelectric conversion layer.
IMAGING DEVICE, STACKED IMAGING DEVICE, AND SOLID-STATE IMAGING APPARATUS
An imaging device includes: a first electrode; a charge storage electrode disposed at a distance from the first electrode; a photoelectric conversion layer in contact with the first electrode and above the charge storage electrode, with an insulating layer between the charge storage electrode and the photoelectric conversion layer; and a second electrode on the photoelectric conversion layer. The portion of the insulating layer between the charge storage electrode and the photoelectric conversion layer includes a first region and a second region, the first region is formed with a first insulating layer, the second region is formed with a second insulating layer, and the absolute value of the fixed charge of the material forming the second insulating layer is smaller than the absolute value of the fixed charge of the material forming the first insulating layer.
IMAGING DEVICE AND SOLID-STATE IMAGE SENSOR
An imaging device includes a first electrode, a charge accumulating electrode arranged with a space from the first electrode, an isolation electrode arranged with a space from the first electrode and the charge accumulating electrode and surrounding the charge accumulating electrode, a photoelectric conversion layer formed in contact with the first electrode and above the charge accumulating electrode with an insulating layer interposed therebetween, and a second electrode formed on the photoelectric conversion layer. The isolation electrode includes a first isolation electrode and a second isolation electrode arranged with a space from the first isolation electrode, and the first isolation electrode is positioned between the first electrode and the second isolation electrode.
IMAGING ELEMENT AND IMAGING DEVICE
An imaging element according to an embodiment of the present disclosure includes: a first electrode and a second electrode; a third electrode; a photoelectric conversion layer; and a semiconductor layer. The first electrode and the second electrode are disposed in parallel. The third electrode is disposed to be opposed to the first electrode and the second electrode. The photoelectric conversion layer is provided between the first electrode and second electrode and the third electrode. The photoelectric conversion layer includes an organic material. The semiconductor layer includes a first layer and a second layer that are stacked in order from the first electrode and second electrode side between the first electrode and second electrode and the photoelectric conversion layer. The first layer has a larger value for C5s indicating a contribution ratio of a 5 s orbital to a conduction band minimum than a value of the second layer for C5s. The second layer has a larger value for Evo indicating oxygen deficiency generation energy or a larger value for E.sub.VN indicating nitrogen deficiency generation energy than a value of the first layer for Evo or E.sub.VN.
Imaging device
An imaging device including: a photoelectric converter that generates a signal charge by photoelectric conversion of light; a semiconductor substrate; a charge accumulation region that is an impurity region of a first conductivity type in the semiconductor substrate, the charge accumulation region being configured to receive the signal charge; a first transistor that includes, as a source or a drain, a first impurity region of the first conductivity type in the semiconductor substrate; and a blocking structure that is located between the charge accumulation region and the first transistor. The blocking structure includes a second impurity region of a second conductivity type in the semiconductor substrate, the second conductivity type being different from the first conductivity type, and a first electrode that is located above the semiconductor substrate, the first electrode being configured to be applied with a first voltage.