H01L27/14654

Image device having multi-layered refractive layer on back surface

An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

Image sensor comprising an inter-pixel overflow (IPO) barrier and electronic system including the same

An image sensor includes a substrate having a sensing area, a floating diffusion region arranged in the sensing area, a plurality of photodiodes arranged around the floating diffusion region in the sensing area, and an inter-pixel overflow (IPO) barrier in contact with each of the plurality of photodiodes, the IPO barrier overlapping the floating diffusion region in a vertical direction at a position vertically spaced apart from the floating diffusion region within the sensing area.

Global shutter imaging pixels

A global shutter imaging pixel may have a single source follower transistor. The source follower transistor may be coupled to a floating diffusion region and a charge storage region. In order to read out samples from the charge storage region without including a second source follower transistor in each pixel, the samples may be transferred to floating diffusion regions of adjacent pixels. Alternatively, a transistor may be configured to transfer charge from the charge storage region to the floating diffusion region of the same pixel, thus reusing a single source follower transistor. These types of pixels may be used for correlated double sampling, where a reset charge level and integration charge level are both sampled. These pixels may also operate in a global shutter mode where images are captured simultaneously by each pixel.

IMAGING DEVICE AND CAMERA SYSTEM
20180350862 · 2018-12-06 ·

An imaging device includes a pixel, the pixel including a photoelectric converter which converts light into a signal charge and a charge detection circuit which detects the signal charge. The photoelectric converter includes a photoelectric conversion layer having a first surface and a second surface opposite to the first surface, a pixel electrode on the first surface, a first electrode adjacent to the pixel electrode on the first surface, the first electrode being electrically conductive to the photoelectric conversion layer, and a counter electrode on the second surface, the counter electrode facing the pixel electrode and the first electrode. A shortest distance between the pixel electrode and the first electrode in a plan view is smaller than a shortest distance between the pixel electrode and the first electrode.

HDR skimming photodiode with true LED flicker mitigation

Apparatuses and methods for a skimming photodiode with high dynamic range (HDR) and reduced Light Emitting Diode (LED) flicker in imaging system are disclosed herein. A voltage generator provides a transfer gate voltage to a transfer transistor. The transfer gate voltage is a voltage selected one of a transfer-on, a transfer-off, and a skimming voltage. The transfer transistor transfers charges generated on a Complementary Metal-Oxide-Semiconductor (CMOS) photodiode (PD) to a floating diffusion (FD). The voltage on transfer gate controls the amount of the charges that can be transferred from the PD to the FD. A reset transistor precharges the PD and FD to an AVDD. A first enable transistor controls the amount of charges transferred from the FD to a first capacitor. A second enable transistor controls the amount of charges transferred from the FD to a second capacitor. The first and second enable transistors receive their individual periodical control pulses once activated. Charges collected on the first and second capacitors are transferred to the FD. A source follower transistor amplifies voltage appeared on the FD. A row select transistor sends the amplified voltage to the bitline for signal readout.

Imaging array with improved dynamic range utilizing parasitic photodiodes within floating diffusion nodes of pixels
10128286 · 2018-11-13 · ·

A pixel sensor having a main photodetector and a parasitic photodiode and a method for reading out that pixel sensor are disclosed. The pixel sensor is read by reading a first potential on a floating diffusion node in the pixel sensor while the floating diffusion node is isolated from the main photodiode. The pixel sensor is then exposed to light such that the floating diffusion node and the photodetector are both exposed to the light. A second potential on the floating diffusion node is then readout while the floating diffusion node is isolated from the main photodiode. After the first and second potentials are readout, a third potential on the floating diffusion node is readout. The main photodiode is then connected to the floating diffusion node, and a fourth potential on the floating diffusion node is readout. First and second light intensities are determined from the readout potentials.

Metal shield trenches and metal substrate contacts supported within the premetallization dielectric (PMD) layer of an integrated circuit using a middle end of line (MEOL) process

A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

Image sensor having stacked metal oxide films as fixed charge film

An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

MATRIX SENSOR WITH LOGARITHMIC RESPONSE AND EXTENDED TEMPERATURE OPERATING RANGE
20180278866 · 2018-09-27 ·

A matrix sensor with logarithmic response and extended temperature operating range, including a plurality of active pixels each defined by a photodiode (PD) operating in solar cell mode, the photodiode being formed by a semiconductor junction in a substrate (11), a reverse-biased junction (20) being present at a distance (d), from the junction of the photodiode, that is less than the diffusion length of the charges in the substrate, the reverse-biased junction (20) being produced by a diffusion to a depth (p) greater than that (p) used in the formation of the source or drain of transistors of the sensor, adjacent to the photodiode.

Image Sensor Having Full Well Capacity Beyond Photodiode Capacity
20180278869 · 2018-09-27 ·

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.