The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a vertical transfer gate extending vertically from a front-side of a substrate to a first position within the substrate and a photodiode doped region disposed under and extending laterally toward one side of the vertical transfer gate. A doped lateral isolation region disposed along a top surface of the photodiode doped region, and a doped vertical isolation region disposed along a sidewall of the vertical transfer gate. A doped pixel device well is vertically above the doped lateral isolation region and separated from the vertical transfer gate by the doped vertical isolation region. A pixel device is disposed within the doped pixel device well at the front-side of the substrate.

An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

An image sensor includes a substrate having a sensing area, a floating diffusion region arranged in the sensing area, a plurality of photodiodes arranged around the floating diffusion region in the sensing area, and an inter-pixel overflow (IPO) barrier in contact with each of the plurality of photodiodes, the IPO barrier overlapping the floating diffusion region in a vertical direction at a position vertically spaced apart from the floating diffusion region within the sensing area.

The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode and a pixel device. The photodiode is arranged within the substrate away from a front-side of the substrate. A pixel device is disposed at the front-side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Comparing to previous image sensor designs, where an upper portion of the photodiode is commonly arranged at a top surface of a front-side of the substrate, now the photodiode is arranged away from the top surface and leaves more room for pixel devices. Thus, a larger pixel device can be arranged in the sensing pixel, and short channel effect and noise level can be improved.

A solid-state imaging device according to the disclosure includes a semiconductor substrate which has a main surface having a plurality of photosensitive regions, and an insulating film which is provided on the main surface of the semiconductor substrate. When the main surface of the semiconductor substrate is taken as a reference surface, a thickness of the insulating film from the reference surface is 0.5 μm or more, a surface (a main surface) of the insulating film on the side opposite to the main surface is a surface having flatness, and a plurality of types of bottom surfaces of which depths from the reference surface are different from each other are provided on the main surface of the semiconductor substrate in the photosensitive regions.

A solid-state image sensor includes a pixel array including pixel cells arranged in a matrix. Each of the pixel cells includes an avalanche photodiode, a floating diffusion which accumulates charges, a transfer transistor which connects a cathode of the avalanche photodiode to the floating diffusion, a first reset transistor for resetting charges collected in the cathode of the avalanche photodiode, a second reset transistor for resetting charges accumulated in the floating diffusion, an amplification transistor for converting a charge amount of charges accumulated in the floating diffusion into a voltage, a memory which accumulates charges, and a count transistor which connects the floating diffusion to the memory.

The semiconductor photodetector device comprises a substrate of semiconductor material of a first type of electric conductivity, an epitaxial layer of an opposite second type of electric conductivity, a further epitaxial layer of the first type of electric conductivity and photodetectors. The epitaxial layer functions as a shielding layer for charge carriers (e.sup.−, h.sup.+ generated by radiation that is incident from a rear side opposite the photodetectors.

An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

A FinFET pixel architecture for an image sensor is disclosed. Specific implementations of a pixel of an image sensor may include a photodiode region coupled with a transfer region coupled with one or more fin field-effect transistors (FinFETs). The one or more FinFETs may be one of a transfer transistor, a storage gate, a reset transistor, a source follower transistor, a row select transistor, or an anti-blooming gate.

A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.