One or more systems and/or methods are disclosed for building a relief print generator with no bezel. An electrode layer having more than one electrode can be used in an electrode-based, electro-luminescence component of the relief print generator. The respective electrodes may be connected to power sources with different voltage phases. An electrical circuit can be created between a biometric object and more than one electrode in the electrode layer when the biometric object contacts a surface of the generator. The electro-luminescent component can be activated by electrical charge and emit light indicative of a relief print of the biometric object. A contact electrode outside the electrode layer may not be used, which may allow for the removal of a bezel from an example device.

A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Color mixing between pixels of different colors is suppressed. A solid-state imaging device includes: a semiconductor layer including a plurality of photoelectric conversion sections partitioned by an isolation region; a shared on-chip lens arranged on a light incident surface side of the semiconductor layer, the shared on-chip lens being shared by the photoelectric conversion sections adjacent to each other with the isolation region interposed between the photoelectric conversion sections, and having a condensing point positioned in the isolation region; and a concave portion provided in an upper portion of the photoelectric conversion sections that share the shared on-chip lens on the light incident surface of the semiconductor layer.

An image pickup device having a pixel region in which pixels are arranged, and in which a multilayer wiring structure is disposed. Each pixel includes a photoelectric conversion unit, a charge accumulation unit, a floating diffusion, a light shielding portion covering the charge accumulation unit and opening above the photoelectric conversion unit, and a waveguide which overlaps at least partially a portion at which the light shielding portion opens in a plan view. The device includes an insulating film disposed below the optical waveguide. The insulating film has a refractive index higher than that of an interlayer insulating film. The insulating film is disposed closer to the photoelectric conversion unit than to the lowermost wiring layer among wiring layers of the multilayer wiring structure. The insulating film extends to a portion above the light shielding portion. The insulating film is wider than a lower portion of the optical waveguide.

A sensing device includes a flexible substrate, a reflective layer, a planarization layer, plural switching elements and plural sensing elements. The flexible substrate has plural recesses on a surface. The reflective layer is located on the flexible substrate and conforms to an inner surface of the plural recesses. The planarization layer is disposed on the reflective layer. The plural switching elements are disposed on the planarization layer. The plural sensing elements are disposed on the planarization layer and electrically connected to the plural switching elements respectively. A method for fabricating a sensing device is also provided.

The present disclosure describes a semiconductor device having radiation-sensing regions separated by trench isolation structures. The semiconductor structure includes a first trench fill structure on a substrate and a second trench fill structure on the substrate. The first trench fill structure has a first width and a convex bottom surface. The second trench fill structure has a concave bottom surface and a second width greater than the first width.

Methods for forming a deep trench isolation (DTI) structure with only two interfaces. In some embodiments, a method of forming a deep trench isolation structure may include etching a trench with a high aspect ratio into a substrate material, repairing the surfaces of the trench from damage caused by etching of the trench, growing an epitaxial layer on the surfaces of the trench to form a homogeneous passivation region as part of the substrate material, doping the epitaxial layer with a dopant to form a passivation charge region, performing a charge diffusion process to embed the dopant into the substrate material, forming a conformal liner layer on the homogeneous passivation region in the trench, and filling the trench with an optically reflective material.

A backside-illuminated image sensor and a method of manufacturing the same are disclosed. The backside-illuminated image sensor is capable of improving sensitivity by including a scattering layer in a substrate that may result in incident light having a path greater than the thickness of the substrate and, simultaneously, of additionally enhancing light sensitivity with respect to a specific wavelength or wavelength band of light passing through one of a plurality of different color filters by a varying depth or thickness of the scattering layer for each unit pixel in the image sensor.

A pixel-array substrate includes a semiconductor substrate and a passivation layer. The semiconductor substrate includes a pixel array surrounded by a periphery region. A back surface of the semiconductor substrate forms, in the periphery region, a plurality of first peripheral-trenches extending into the semiconductor substrate. The passivation layer is on the back surface and lines each of the plurality of first peripheral-trenches.

There is provided an imaging device including: a first semiconductor substrate having a first region that includes a photoelectric conversion section and a via portion, a second region adjacent to the first region, a connection portion disposed at the second region, and a second semiconductor substrate, wherein the connection portion electrically couples the first semiconductor substrate to the second semiconductor substrate in a stacked configuration, and wherein a width of the connection portion is greater than a width of the via portion.