A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.

An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a molding layer, a silicon layer on the molding layer, a glass upwardly spaced apart from the silicon layer, and a connection dam coupled to the silicon layer and connecting the silicon layer to the glass. The silicon layer includes a silicon layer body, a silicon layer via extending vertically in the silicon layer body, and a micro-lens array on a top surface of the silicon layer body. A bottom surface of the silicon layer body contacts a top surface of the molding layer. The molding layer includes a molding layer body, a molding layer via that extends vertically in the molding layer body and has electrical connection with the silicon layer via, and a connection ball connected to a bottom surface of the molding layer via.

The present disclosure describes a throughput-scalable image sensing system for analyzing biological or chemical samples is provided. The system includes a plurality of image sensors configured to detect at least a portion of light emitted as a result of analyzing the biological or chemical samples. The plurality of image sensors is arranged on a plurality of wafer-level packaged semiconductor dies of a single semiconductor wafer. Each image sensor of the plurality of image sensors is disposed on a separate packaged semiconductor die of the plurality of packaged semiconductor dies. Neighboring packaged semiconductor dies are separated by a dicing street; and the plurality of packaged semiconductor dies and a plurality of dicing streets are arranged such that the plurality of packaged semiconductor dies can be diced from the single semiconductor wafer as a group.

Restrictions in placement of an antenna for performing transmission and reception of a signal by wireless communication when the antenna is used together with a CSP (Chip Size Package) are eliminated. A semiconductor device includes a chip size package and a substrate. The chip size package includes a semiconductor element. Further, the chip size package includes a connection portion that electrically connects the semiconductor element and an outside to each other. The substrate includes an antenna connected to the connection portion of the chip size package for performing transmission and reception of a signal by wireless communication. With this configuration, the semiconductor device performs transmission and reception of a signal to and from the outside through the antenna provided on the substrate.

An image sensor includes a first substrate having a first surface and a second surface opposite to the first surface. The first substrate includes an active pixel region having a plurality of active pixels. A plurality of lower electrode structures is disposed on the second surface of the first substrate and corresponds to the plurality of active pixels. An upper electrode is disposed on the plurality of lower electrode structures. An organic photoelectric conversion layer is disposed between the plurality of lower electrode structures and the upper electrode. A second substrate is disposed on the first surface of the first substrate. A driving circuit configured to drive the plurality of active pixels is disposed on the second substrate. The plurality of lower electrode structures includes a first barrier layer, a reflective layer disposed on the first barrier layer and a second barrier layer disposed on the reflective layer.

A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion.

A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.

There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.