Patent classifications
H01L27/14698
SENSORS HAVING AN ACTIVE SURFACE
Disclosed in one example is an apparatus including a substrate, a sensor over the substrate including an active surface and a sensor bond pad, a molding layer over the substrate and covering sides of the sensor, the molding layer having a molding height relative to a top surface of the substrate that is greater than a height of the active surface of the sensor relative to the top surface of the substrate, and a lidding layer over the molding layer and over the active surface. The lidding layer and the molding layer form a space over the active surface of the sensor that defines a flow channel.
Germanium metal-contact-free near-IR photodetector
A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at 4 V reverse bias. 3-dB bandwidth is 30 GHz.
SOLID-STATE IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions.
SHORT-WAVE INFRARED DETECTOR ARRAY AND FABRICATION METHODS THEREOF
Disclosed are methods of fabricating short-wave infrared detector arrays including readout and absorption wafers connected by a recrystallized a-Si layer. The absorber wafer includes a SWIR conversion layer with a Ge.sub.1-xSn.sub.x alloy composition. Process steps realize the readout wafer and a portion of the absorption wafer, including bonding the readout wafer and a first portion of the absorption wafer. The a-Si intermediate layer linking the readout wafer and the first portion of the absorption wafer the a-Si intermediate layer is recrystallized by applying heat by a light source. The method assures a temperature profile between the light entrance surface and the CMOS electronic layer of the readout wafer maintaining readout layer temperature <350 C. during recrystallization. After the recrystallization process step the absorption wafer is completed by depositing the SWIR conversion layer. Also disclosed is a SWIR detector array realized by the method and SWIR detector array applications.
IMAGE SENSOR MODULE HAVING PROTECTIVE STRUCTURE THAT BLOCKS INCIDENT LIGHT TO ARRIVE AT BONDING WIRES AND PADS
An image sensor module comprises: a substrate having a first side and second side, the first side being an opposite of the second side, an image sensor attached to the first side of the substrate, bonding wires to bond the image sensor to pads on the first side of the substrate, a protective structure disposed on the first side of the substrate surrounding the image sensor, the bonding wires, and the pads, the protective structure having a dam and a lid, a cover glass disposed on the protective structure, and a set of solder balls attached to the second side of the substrate.
SHORT-WAVE INFRARED DETECTOR AND ITS INTEGRATION WITH CMOS COMPATIBLE SUBSTRATES
Disclosed is a low temperature method of fabrication of short-wave infrared (SWIR) detector arrays (FPA) including a readout wafer and absorption layer connected for improved performances. The absorber layer includes a SWIR conversion layer with a GeSn or SiGeSn alloy. A first series of process steps realizes a CMOS processed readout wafer. A buffer layer is transferred on the readout wafer and annealed at temperatures compatible with the CMOS substrate, achieving a high quality crystalline buffer layer. The method assures a temperature profile between the light entrance surface of the buffer layer, and the readout electronics so the annealing temperature remains compatible with the CMOS. The buffer layer is used for further growth of a GeSn or SiGeSn structure to create the conversion layer and achieve the final structure of the SWIR FPA. Also disclosed is a SWIR FPA detector as realized by such method, and SWIR FPA applications.
Back-side deep trench isolation structure for image sensor
The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
Bond pad structure for bonding improvement
A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.
GERMANIUM-SILICON LIGHT SENSING APPARATUS
A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including growing a germanium-silicon layer on a semiconductor donor wafer; defining pixels of the image sensor array on the germanium-silicon layer; defining a first interconnect layer on the germanium-silicon layer, wherein the interconnect layer includes a plurality of interconnects coupled to the first group of photodiodes and the second group of photodiodes; defining integrated circuitry for controlling the pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer, wherein the second interconnect layer includes a plurality of interconnects coupled to the integrated circuitry; and bonding the first interconnect layer with the second interconnect layer.
Semiconductor surface passivation
A new process that enables void-free direct-bonded MBE-passivated large-format image sensors is disclosed. This process can be used to produce thin large-area image sensors for UV and soft x-ray imaging. Such devices may be valuable in future astronomy missions or in the radiology field. Importantly, by controlling the hydrogen concentration in the silicon oxide layers of the image sensor and the support wafer, voids in the bonding interface can be significantly reduced or eliminated. This process can be applied to any wafer that includes active circuitry and requires a second wafer, such as a support wafer.