The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

A method of producing an epitaxial silicon wafer includes irradiating a surface of a silicon wafer with a beam of cluster ions containing SiH.sub.x ions (at least one of the integers 1 to 3 is selected as x of the SiH.sub.x ions) and C.sub.2H.sub.y ions (at least one of the integers 2 to 5 is selected as y of the C.sub.2H.sub.y ions) to form a modified layer that is located in a surface layer portion of the silicon wafer and that contains as a solid solution of the constituent elements of the cluster ion beam, and further includes forming a silicon epitaxial layer on the modified layer of the silicon wafer. The dose of the SiH.sub.x ions is 1.5×10.sup.14 ions/cm.sup.2 or more.

The present disclosure provides a method for forming a backside illumination CMOS image sensor, including: providing a first substrate having a first surface and a second surface opposite to each other; forming a photoelectric epitaxial layer on the second surface, wherein the photoelectric epitaxial layer has a third surface and a fourth surface opposite to each other, and the second surface is adjacent to the third surface, wherein the photoelectric epitaxial layer is includes a groove extending from the fourth surface to the third surface, and the photoelectric epitaxial layer includes a plurality of first doped areas and a plurality of second doped areas surrounding the plurality of first doped areas respectively; forming a device layer after forming the groove and the photoelectric epitaxial layer; and forming an isolation layer in the groove. The method can reduce generation of dark current and improve performance of the CMOS image sensor.

A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including growing a germanium-silicon layer on a semiconductor donor wafer; defining pixels of the image sensor array on the germanium-silicon layer; defining a first interconnect layer on the germanium-silicon layer, wherein the interconnect layer includes a plurality of interconnects coupled to the first group of photodiodes and the second group of photodiodes; defining integrated circuitry for controlling the pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer, wherein the second interconnect layer includes a plurality of interconnects coupled to the integrated circuitry; and bonding the first interconnect layer with the second interconnect layer.

A method of fabricating an image sensor includes providing a semiconductor substrate having a first surface and a second surface that are opposite to each other. A mask pattern is formed on the first surface. The mask pattern has an opening. A first fluid is supplied in the opening. The first fluid is vaporized to remove the first fluid on the semiconductor substrate. An etching process is performed using the mask pattern to form a pixel isolation trench extending from the first surface towards the second surface. A second fluid is supplied in the pixel isolation trench. The second fluid is replaced in the pixel isolation trench with a third fluid. The third fluid is vaporized. The third fluid has a surface tension that is lower than a surface tension of the first fluid.

A fingerprint sensor has an array of microlenses formed on an upper surface of a transparent substrate; with a lower surface of the transparent substrate bonded to an upper surface of a fingerprint image sensor integrated circuit. In embodiments, it includes one or two filter layers on the lower surface of the transparent substrate, and may also include masked black baffle layers on one or more of the upper and lower surface of the transparent substrate. The sensor is made by forming the microlenses and black baffle layers on the transparent substrate, then aligning the transparent substrate to a wafer of fingerprint sensor integrated circuits and bonding the transparent substrate to the wafer, then dicing the wafer into individual fingerprint sensors.

A boron layer may be formed as a passivation layer in a recess in which a deep trench isolation structure (DTI) structure is to be formed. The boron layer results in formation of a boron-silicon interface between the DTI structure and a photodiode of a pixel sensor included in a pixel array. The boron-silicon interface functions as a diode junction, which resists penetration of photons into the DTI structure. This reduces and/or minimizes photon transmission through the DTI structure, which reduces and/or minimizes optical crosstalk between pixel sensors of the pixel array.

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.

A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.