Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

A solid-state image pickup device according to an embodiment is a solid-state image pickup device including a first pixel row, a second pixel row, and a third pixel row that are arranged in a horizontal direction. In the solid-state image pickup device, a first control pulse for transferring charges of first accumulation portions of the fourth and sixth CCD registers in a vertical direction perpendicular to the horizontal direction and a second control pulse for transferring charges of second accumulation portions of the fourth and sixth CCD registers in the horizontal direction are input to the fourth and sixth CCD registers such that an Hi period of the first control pulse and an Hi period of the second control pulse do not overlap each other in a timing period in which charges accumulated in the first, second, and third pixel rows are transferred.

A back-illuminated solid-state imaging device includes a semiconductor substrate, a shift register, and a light-shielding film. The semiconductor substrate includes a light incident surface on the back side and a light receiving portion generating a charge in accordance with light incidence. The shift register is disposed on the side of a light-detective surface opposite to the light incident surface of the semiconductor substrate. The light-shielding film is disposed on the side of the light-detective surface of the semiconductor substrate. The light-shielding film includes an uneven surface opposing the light-detective surface.

An imaging device includes a semiconductor substrate, pixels, a charge detector, charge storage portions, an output gate portion and a shift gate portion. The pixels and the charge detector are provided in the semiconductor substrate. The charge storage portions are provided on the charge detector side of the pixels, and linked to the pixels. The output gate portion is positioned between the charge detector and the charge storage portions, and includes charge transfer channels extending in a radial configuration in directions from the charge detector toward the pixels. The shift gate portion is positioned between one charge storage portion and one charge transfer channel. The shift gate portion includes a gate electrode provided on the semiconductor substrate. A planar configuration of the gate electrode has a side orthogonal to the extending direction of the one charge transfer channels, the side being most proximal to the one charge transfer channel.

A solid-state image pickup device according to an embodiment is a solid-state image pickup device including a first pixel row, a second pixel row, and a third pixel row that are arranged in a horizontal direction. In the solid-state image pickup device, a first control pulse for transferring charges of first accumulation portions of the fourth and sixth CCD registers in a vertical direction perpendicular to the horizontal direction and a second control pulse for transferring charges of second accumulation portions of the fourth and sixth CCD registers in the horizontal direction are input to the fourth and sixth CCD registers such that an Hi period of the first control pulse and an Hi period of the second control pulse do not overlap each other in a timing period in which charges accumulated in the first, second, and third pixel rows are transferred.

A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

A solid-state imaging device of an embodiment includes plural first transfer gate electrodes, plural second transfer gate electrodes, and plural fixed gate electrodes. The first transfer gate electrodes are such that the respective first transfer gate electrodes are placed in a charge transfer unit to correspond to single light receiving sections, and a control signal 1 is applied. The second transfer gate electrodes are such that the respective second transfer gate electrodes are placed in a charge transfer unit to correspond to the single light receiving sections, and a control signal 2 that differs in phase from the control signal 1 for transferring plural charges is applied. The respective fixed gate electrodes are such that the respective fixed gate electrodes are placed between the first and the second transfer gate electrodes corresponding to the single light receiving sections in the charge transfer unit, and a fixed voltage is applied.

A time-of-flight (TOF) pixel includes a semiconductor material and a photogate disposed proximate to a frontside of the semiconductor material. The photogate is positioned to transfer charge in the semiconductor material toward the frontside in response to a voltage applied to the photogate. A floating diffusion is disposed in the semiconductor material proximate to the frontside of the semiconductor material, and one or more virtual phase implants is disposed in the semiconductor material proximate to the frontside of the semiconductor material. At least one of the one or more virtual phase implants extend laterally from under the photogate to the floating diffusion to transfer the charge to the floating diffusion.

A solid-state imaging device includes: pixels arranged in a matrix on a semiconductor substrate. Each of the pixels includes: a photoelectric converter that converts received light into a signal charge; at least one read gate that reads the signal charge from the photoelectric converter; charge accumulators that each accumulate the signal charge read by the at least one read gate; and a charge holder that receives, from one of the charge accumulators, transfer of the signal charge accumulated in the charge accumulator, holds the signal charge, and transfers, to one of the charge accumulators, the signal charge held, each of the charge accumulators includes a part of a transfer channel and a part of a transfer electrode overlapping with the part of the transfer channel in a planar view of the semiconductor substrate, and the transfer channel per one pixel comprises transfer channels.