In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.

A semiconductor device according to as embodiment includes a semiconductor layer that has first and second plane and includes first-conductivity-tom e first semiconductor region, second-conductivity-tom e second semiconductor region between the first semiconductor region and the first plane, first-conductivity-type third semiconductor region between the second semiconductor region and the first plane and has a lower first-conducivity type impurity concentration than the first semiconductor region, and second-conductivity-type fourth semiconductor region between the third semiconductor region. and the first plane and has a higher second-conductivity-type impurity concentration than the second semiconductor region; a first electrode on a side of the first plane of the semiconductor layer and is electrically connected to the third semiconductor region and the fourth semiconductor region; and a second electrode on a side of the second plane of the semiconductor layer, is electrically connected to the first semiconductor region, and is not electrically connected. to the second semiconductor region.

A stacked integrated circuit encompasses a lower chip including a lower semiconductor element and an upper surface-electrode electrically connected to an upper main-electrode region of the lower semiconductor element, the upper main-electrode region is located on an upper-surface side of the lower semiconductor element; and an upper chip including an upper semiconductor element and a lower surface-electrode electrically connected to a lower main-electrode region of the upper semiconductor element, the lower main-electrode region is located on a lower-surface side of the upper semiconductor element, the lower surface-electrode is metallurgically in contact with the upper surface-electrode.

A semiconductor device has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first conductive layer disposed on a main surface of the first semiconductor region, and a second conductive layer disposed on a main surface of the second semiconductor region. The first conductive layer has a first diffusion layer of the first conductivity type, a plurality of second diffusion layers of the first conductivity type, the second diffusion layers having higher impurity concentration than the first diffusion layer, and a plurality of third diffusion layers of the first conductivity type that are included in the first semiconductor region, or are arranged apart from one another to contact the first and second semiconductor regions, the third diffusion layers being arranged apart from the plurality of second diffusion layers and having higher impurity concentration than the first diffusion layer.

A p anode layer is formed on one main surface of an n.sup. drift layer. N.sup.+ cathode layer having an impurity concentration more than that of the n.sup. drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n.sup.+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n.sup.+ cathode layer and p anode layer is formed in the n.sup. drift layer. Resistivity .sub.0 of the n.sup. drift layer satisfies 0.12V.sub.0.sub.00.25V.sub.0 with respect to rated voltage V.sub.0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.810.sup.11 atoms/cm.sup.2 and equal to or less than 1.010.sup.12 atoms/cm.sup.2.

A power device, which has a Field Stop (FS) layer based on a semiconductor substrate between a collector region and a drift region in an FS-IGBT structure. The FS layer includes multiple implants for improved functionality of the power device.

Provided is a Schottky electrode structure, the electrode structure including: a first N-type semiconductor layer; a P-type semiconductor layer covering the first N-type semiconductor layer; a second N-type semiconductor layer or a semi-insulting semiconductor layer covering the P-type semiconductor layer. By using the Schottky electrode structure, the reverse withstand voltage of the diode can be effectively improved, and the reliability of the diode is effectively improved.

Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.

A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.