A metal-oxide-semiconductor device can include: a base layer; a source region extending from an upper surface of the base layer to internal portion of the base layer and having a first doping type; a gate structure located on the upper surface of the base layer and at least exposing the source region, and a semiconductor layer located on the upper surface of the base layer and having the first doping type, where the semiconductor layer is used as a partial withstand voltage region of the device, and the source region is located at a first side of the gate structure, the semiconductor layer is located at a second side of the gate structure, and the first side and the second side of the gate structure are opposite to each other.

Embodiments of the disclosure provide a bandgap reference circuit, including: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region.

A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms.

The embodiments of the invention provides a semiconductor device and a method for manufacturing it The semiconductor device provided by the embodiments of the invention comprises: a first electrode layer; a substrate layer positioned on the first electrode layer; an epitaxy layer positioned on the substrate layer and comprising a first surface far from the substrate layer; a plurality of well regions disposed by extending from the first surface into the epitaxy layer and orthographic projections thereof on the first surface are spaced from each other; a second electrode layer, comprising first metal layers, each disposed between adjacent two of the well regions on the first surface and forms a Schottky contact with the epitaxy layer, wherein the Schottky contact has variable barrier height. The semiconductor device provided by the embodiments of the invention may improve the forward conduction ability without affecting the reverse blocking ability.

A gallium nitride high electron mobility transistor and a formation method therefor are provided. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas. The high electron mobility transistor has a higher breakdown voltage.

A semiconductor device includes a protected element and a connection section. The protected element is configured including a diode having an anode region and a cathode region. The diode is arranged on an active layer of a substrate including the active layer formed over a conductive substrate-support with an insulation layer interposed therebetween. The connection section electrically connects the cathode region of the protected element to the substrate-support.

A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

An IGBT and a manufacturing method therefor, wherein a target region in the IGBT is doped with first ions; the target region comprises at least one of a P-type substrate (11), a P-type well region (13), and a P-type source region (14); and the diffusion coefficient of the first ions is greater than the diffusion coefficients of boron ions. A PN junction formed by means of the present invention is a gradual junction, thereby improving breakdown voltage, shortening turn-off time, and improving anti-latch capability.

A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

A semiconductor device includes first and second layers and first and second electrodes. The first layer has a first semiconductor containing an impurity of a first conductivity type. The second layer is in contact with the first layer and has a second semiconductor containing the impurity at a lower concentration than the first semiconductor. The first electrode is in contact with a first surface of the first layer. The second electrode is in contact with a second surface of the second layer. The second layer further has first and second trenches. The first trench has therein a third electrode connected to the second electrode. The second trench is located closer to an outer perimeter portion of the second layer than the first trench and has therein a fourth electrode connected to the second electrode. An entire outer perimeter end of the second electrode is in contact with the fourth electrode.