A semiconductor device includes a first semiconductor layer, a first electrode above and electrically connected to the first semiconductor layer, a second electrode above the first semiconductor layer and electrically connected to the first semiconductor layer, a first insulating layer above the first semiconductor layer between the first and second electrodes, and a third electrode. The second electrode is spaced from the first electrode along the first semiconductor layer. The third electrode includes a first portion above the first insulating layer between the first and second electrodes, and a second portion between the first portion and the second electrode and extending from the first portion in the direction of, and spaced from, the second electrode. The distance between the first semiconductor layer and an adjacent curved surface of the second portion gradually increases from the first portion to the end of the second portion distal the first portion.

A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof

Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n.sup.− drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.

An object is to provide a semiconductor device in which the area of inspection wiring for detecting chipping, cracks, or the like is narrowed. The semiconductor device includes a semiconductor substrate including an effective region including a semiconductor element and an ineffective region provided on a circumference of the effective region on a front surface thereof, and a rear surface electrode on a rear surface thereof; and inspection wiring provided in the ineffective region on the front surface of the semiconductor substrate so as to surround an outer periphery of the effective region. The inspection wiring is electrically connected to the rear surface electrode in such a manner that one end of the inspection wiring is in contact with the semiconductor layer which is provided in the ineffective region on the front surface of the semiconductor substrate and electrically connected to the rear surface electrode.

A semiconductor device includes; a semiconductor substrate including a major surface; a first diffusion region in the major surface in a main cell region; a second diffusion region in the major surface in a terminal region; an insulating film on the major surface and having first and second contact holes on the first and second diffusion regions respectively; a first electrode in the first contact hole and connected to the first diffusion region; a second electrode in the second contact hole and connected to the second diffusion region; a semi-insulating film covering the second electrode; and a third electrode on the first electrode, wherein the first and second electrodes are made of the same material, the first electrode does not completely fill the first contact hole, the second electrode completely fills the second contact hole, and the third electrode completely fills the first contact hole.

An IGBT region includes: an n-type carrier accumulation layer provided to be in contact with the n.sup.−-type drift layer on the first main surface side of the n.sup.−-type drift layer and having a higher n-type impurity concentration than the n.sup.−-type drift layer, a p-type base layer provided between the n-type carrier accumulation layer and the first main surface, an n.sup.+-type emitter layer selectively provided in a surface layer portion of the p-type base layer, and a gate electrode provided to face the n.sup.+-type emitter layer and the p-type base layer with an interposition of an insulating film. A diode region includes a p-type anode layer provided between the n.sup.−-type drift layer and the first main surface and provided to a position deeper from the first main surface than a boundary between the n-type carrier accumulation layer and the n.sup.−-type drift layer.

Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.