Semiconductor devices, and in particular semiconductor devices for improved resistance measurements and related methods are disclosed. Contact structures for semiconductor devices are disclosed that provide access to resistance measurements with reduced influence of testing-related resistances, thereby improving testing accuracy, particularly for semiconductor devices with low on-resistance ratings. A semiconductor device may include an active region and an inactive region that is arranged along a perimeter of the active region. The semiconductor device may be arranged with a topside contact to provide access for resistance measurements, for example Kelvin-sensing resistance measurements. Related methods include performing resistance measurements from a topside of the semiconductor device, even when the active region of the semiconductor device forms a vertical contact structure.

A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer is provided below the first semiconductor layer. The diode trench gate includes a diode trench insulation film formed along, out of the inner wall of the trench, a lower side wall and a bottom that are located below an upper side wall located on the upper end side of the trench. The diode trench gate includes a diode trench electrode provided inside the trench. The electrode layer covers the upper side wall of the trench. The first semiconductor layer is in contact with the electrode layer on the upper side wall of the trench.

An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

An insulating film is formed on a main surface of a semiconductor substrate constituting a semiconductor device so as to cover a field plate portion, a metal pattern thicker than the field plate portion is formed on the insulating film, and a protective film is formed on the insulating film so as to cover the metal pattern. The field plate portion is made of polycrystalline silicon, and the insulating film is composed of a stacked film of one or more silicon nitride films and one or more silicon oxide films.

A semiconductor device including a semiconductor substrate, a parallel pn layer and a device structure provided in the semiconductor substrate, first and second electrodes respectively provided at two main surfaces of the semiconductor substrate, the first electrode being electrically connected to the device structure. The parallel pn layer includes first-conductivity-type column regions and second-conductivity-type column regions that are adjacently disposed and repeatedly alternate with one another in a first direction parallel to the first main surface, that each extend in a second direction parallel to the first main surface and orthogonal to the first direction, and that are of a same impurity concentration. A portion of the second-conductivity-type column regions is shorter than the rest thereof. The parallel pn layer has a first portion and a second portion respectively closer to the first and second main surfaces, the first portion being more p-rich, and less n-rich, than the second portion.

A semiconductor device wherein a hydrogen concentration distribution has a first hydrogen concentration peak and a second hydrogen concentration peak and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak in a depth direction, wherein the first hydrogen concentration peak and the first donor concentration peak are placed at a first depth and the second hydrogen concentration peak and the second donor concentration peak are placed at a second depth deeper than the first depth relative to the lower surface is provided.

A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.

A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.

A metal-oxide semiconductor field effect transistor (MOSFET) includes a substrate and a well over the substrate, the well including dopants of a first conductivity-type. The well includes an anti-punch-through (APT) layer at an upper section of the well, the APT layer including the dopants of the first conductivity-type and further including carbon. The MOSFET further includes a source feature and a drain feature adjacent the APT layer, being of a second conductivity-type opposite to the first conductivity-type. The MOSFET further includes multiple channel layers over the APT layer and connecting the source feature to the drain feature, wherein the multiple channel layers are vertically stacked one over another. The MOSFET further includes a gate wrapping around each of the channel layers, such as in a gate-all-around device, wherein a first portion of the gate is disposed between a bottommost one of the channel layers and the APT layer.