An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first III-nitride layer, a second III-nitride layer, a first contact layer, a second contact layer, a structure, and a gate layer. The second III-nitride layer is in direct contact with the first III-nitride layer. The first contact layer and the second contact layer are disposed over the second III-nitride layer. The structure is adjacent to an interface of the first III-nitride layer and the second III-nitride layer, and a material of the structure is different from a material of the first III-nitride layer or a material of the second III-nitride layer. The gate layer is disposed between the first contact layer and the second contact layer.

A MOSFET includes a semiconductor substrate, which has a body and an upper layer. The upper layer is doped differently than the body. The body and the upper layer are of a same crystal structure and orientation. The MOSFET also includes a p-type FET on the upper layer of the substrate. The p-type FET includes p-doped source/drain structures that sandwich one or more channels and a p gate stack with a p-type work function metal. In one or more embodiments, the p-doped source/drain structures are of the same crystal structure and orientation as the upper layer of the substrate and directly contact the upper layer of the substrate. In one or more embodiments, the upper layer of the substrate is doped differently than the p-doped source/drain structures, such that the p-doped source/drain structures and the upper layer of the substrate form pn-type diodes.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer disposed above the substrate; a second nitride semiconductor layer disposed above the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a third nitride semiconductor layer selectively disposed above the second nitride semiconductor layer and containing a p-type first impurity element; a high resistance region disposed in the third nitride semiconductor layer, the high resistance region containing a second impurity element and having a specific resistance higher than a specific resistance of the third nitride semiconductor layer; and a gate electrode disposed above the high resistance region, wherein an end of the high resistance region is inside a surface end of the third nitride semiconductor layer.