An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

A light sensitive semiconductor structure including a pn-junction in a silicon substrate. The pn-junction includes a central part and an edge part around surrounding the central part, the edge part being in contact with a surface of the silicon substrate. The structure further includes a plasma shielding structure covering at least a depletion width of the pn-junction over at least a part of the edge part where the edge part contacts the surface of the silicon substrate.

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments extending in parallel along the first direction; and a protection structure over the substrate and at least partially overlaps the gate electrode.

There is provided a vertical high-electron-mobility transistor, HEMT (100), comprising: a drain contact (410), a nanowire layer (500) arranged on the drain contact (410) and comprising at least one vertical nanowire (510) and a supporting material (520) laterally enclosing the at least one vertical nanowire (510), a heterostructure (600) arranged on the nanowire layer and comprising an AIGaN-layer (610) and a GaN-layer (620) together forming a heterojunction, at least one source contact (420a, 420b) in contact with the heterostructure (600), and a gate contact (430) in contact with the heterostructure (600), arranged above the at least one vertical nanowire (510), wherein the at least one vertical nanowire (510) is forming an electron transport channel between the drain contact and the heterostructure. There is also provided a method for producing a vertical HEMT (100).

A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

A semiconductor device includes a source region and a drain region formed in a substrate and having different conductivity types, an insulating film formed between the source region and the drain region, a deep well region formed under the insulating film, and a pinch-off region formed under the insulating film and having a same conductivity type as the deep well region, wherein a depth of a bottom surface of the pinch-off region is different from a depth of a bottom surface of the deep well region.

A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.

A vertical field effect transistor, including a drift region having a first conductivity type, a trench structure on or above the drift region, a shielding structure, and a source/drain electrode. The trench structure includes at least one side wall at which a field effect transistor (FET) channel region is formed. The FET channel region includes a III-V heterostructure for forming a two-dimensional electron gas at a boundary surface of the III-V heterostructure. The shielding structure is situated laterally adjacent to the at least one side wall of the trench structure and extends vertically into the drift region or vertically further in the direction of the drift region than the trench structure. The shielding structure has a second conductivity type that differs from the first conductivity type. The source/drain electrode is electroconductively connected to the III-V heterostructure of the trench structure and to the shielding structure.

A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.