A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first III-nitride layer, a second III-nitride layer, a first contact layer, a second contact layer, a structure, and a gate layer. The second III-nitride layer is in direct contact with the first III-nitride layer. The first contact layer and the second contact layer are disposed over the second III-nitride layer. The structure is adjacent to an interface of the first III-nitride layer and the second III-nitride layer, and a material of the structure is different from a material of the first III-nitride layer or a material of the second III-nitride layer. The gate layer is disposed between the first contact layer and the second contact layer.

A semiconductor device is proposed. The semiconductor device includes a semiconductor body including a first main surface. A plurality of trench electrode structures extend in parallel along a first lateral direction. A first one of the plurality of trench electrode structures includes a gate electrode. A gate contact is electrically connected to the gate electrode in a gate contact area. The gate contact area is arranged in a first section along the first lateral direction. An isolation structure is arranged between the gate contact and the semiconductor body in the gate contact area. A bottom side of the isolation structure is arranged between a bottom side of the first one of the plurality of trench electrode structures and the first main surface along a vertical direction. The gate contact extends up to or below the first main surface along the vertical direction.

In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.

A structure and method for guarding a high voltage region at a semiconductor surface from a low voltage region at the semiconductor surface. The structure comprising at least two trenches between the high and low voltage regions to isolate the high voltage region from the low voltage region. The trenches are spaced apart so as to define a sub-region therebetween. To prevent breakdown across the trenches, an intermediate voltage, i.e., of a value between the voltages of the high and low voltage regions, is applied to the sub-region so as to reduce the voltage drop across each trench. Preferably this is achieved by providing an integrated voltage divider circuit that connects between the high and low voltage regions and has an output connected to the sub-region by which the intermediate voltage is applied to the sub-region.

A vertical field-effect transistor. The vertical field-effect transistor has: A first semiconductor layer, which has a p-type conductivity, on or over a drift region; a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure; a source-drain electrode which is electroconductively connected to the III-V-heterostructure; and a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode, and at least the region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region within a semiconductor substrate material; a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

A vertical field-effect transistor. The vertical field-effect transistor includes: a drift area; a first semiconductor fin on or above the drift area and electrically conductively connected thereto; a plurality of second semiconductor fins on or above the drift area, the plurality of second semiconductor fins being formed connected electrically nonconductively to the drift area, the plurality of second semiconductor fins being situated laterally adjacent to at least one side wall of the first semiconductor fin and being electrically conductively connected thereto; and a source/drain electrode, which is electrically conductively connected to the plurality of second semiconductor fins.